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Commit 0fb9e668 by Michael Meissner Committed by Michael Meissner
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constraints.md (wG constraint): Delete, no longer used. 

2018-07-27  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/constraints.md (wG constraint): Delete, no longer
	used.
	* config/rs6000/predicates.md (p9_fusion_reg_operand): Rename
	predicate to reflect toc fusion has been deleted.
	(toc_fusion_mem_raw): Delete, no longer used.
	(toc_fusion_mem_wrapped): Likewise.
	* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete toc
	fusion mask bit.
	* config/rs6000/rs6000-protos.h (fusion_wrap_memory_address):
	Delete, no longer used.
	* config/rs6000/rs6000.c (struct rs6000_reg_addr): Delete fields
	meant to be used for toc fusion.
	(rs6000_debug_print_mode): Delete toc fusion debugging.
	(rs6000_debug_reg_global): Likewise.
	(rs6000_init_hard_regno_mode_ok): Delete setting up fields for toc
	fusion and secondary reload support that were never used.
	(rs6000_option_override_internal): Delete TOC fusion, that was only
	partially defined, and it did not work unless you also used the
	-mcmodel= switch.
	(rs6000_legitimate_address_p): Delete TOC fusion support.
	(rs6000_opt_masks): Likewise.
	(fusion_wrap_memory_address): Delete function, no longer used.
	(fusion_split_address); Delete TOC fusion support.
	* config/rs6000/rs6000.h (TARGET_TOC_FUSION_INT): Delete, no
	longer used with toc fusion being deleted.
	(TARGET_TOC_FUSION_FP): Likewise.
	* config/rs6000/rs6000.md (UNSPEC_FUSION_ADDIS): Delete TOC fusion
	UNSPEC.
	(toc fusion spliter): Delete TOC fusion support.
	(toc_fusionload_<mode>): Likewise.
	(toc_fusionload_di): Likewise.
	(fusion_gpr_load_<mode>): Delete generator function, this insn no
	longer needs to be named.  Rename predicate to delete TOC fusion.
	(fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load): Likewise.
	(fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store): Likewise.
	(fusion_vsx_<P:mode>_<GPR_FUSION:mode>_load): Likewise.
	(fusion_vsx_<P:mode>_<GPR_FUSION:mode>_store): Likewise.
	(p9 fusion peephole2s): Rename predicate to delete TOC fusion.

From-SVN: r263039
parent 96a54a49
Showing with 57 additions and 123 deletions
gcc/ChangeLog
2018-07-27 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/constraints.md (wG constraint): Delete, no longer
used.
* config/rs6000/predicates.md (p9_fusion_reg_operand): Rename
predicate to reflect toc fusion has been deleted.
(toc_fusion_mem_raw): Delete, no longer used.
(toc_fusion_mem_wrapped): Likewise.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete toc
fusion mask bit.
* config/rs6000/rs6000-protos.h (fusion_wrap_memory_address):
Delete, no longer used.
* config/rs6000/rs6000.c (struct rs6000_reg_addr): Delete fields
meant to be used for toc fusion.
(rs6000_debug_print_mode): Delete toc fusion debugging.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Delete setting up fields for toc
fusion and secondary reload support that were never used.
(rs6000_option_override_internal): Delete TOC fusion, that was only
partially defined, and it did not work unless you also used the
-mcmodel= switch.
(rs6000_legitimate_address_p): Delete TOC fusion support.
(rs6000_opt_masks): Likewise.
(fusion_wrap_memory_address): Delete function, no longer used.
(fusion_split_address); Delete TOC fusion support.
* config/rs6000/rs6000.h (TARGET_TOC_FUSION_INT): Delete, no
longer used with toc fusion being deleted.
(TARGET_TOC_FUSION_FP): Likewise.
* config/rs6000/rs6000.md (UNSPEC_FUSION_ADDIS): Delete TOC fusion
UNSPEC.
(toc fusion spliter): Delete TOC fusion support.
(toc_fusionload_<mode>): Likewise.
(toc_fusionload_di): Likewise.
(fusion_gpr_load_<mode>): Delete generator function, this insn no
longer needs to be named. Rename predicate to delete TOC fusion.
(fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load): Likewise.
(fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store): Likewise.
(fusion_vsx_<P:mode>_<GPR_FUSION:mode>_load): Likewise.
(fusion_vsx_<P:mode>_<GPR_FUSION:mode>_store): Likewise.
(p9 fusion peephole2s): Rename predicate to delete TOC fusion.
2018-07-27 Kelvin Nilsen <kelvin@gcc.gnu.org>
* doc/extend.texi (Basic PowerPC Built-in Functions Available on
......
gcc/config/rs6000/constraints.md
......@@ -157,11 +157,6 @@
"Memory operand suitable for power9 fusion load/stores"
(match_operand 0 "fusion_addis_mem_combo_load"))
;; Fusion gpr load.
(define_memory_constraint "wG"
"Memory operand suitable for TOC fusion memory references"
(match_operand 0 "toc_fusion_mem_wrapped"))
(define_register_constraint "wH" "rs6000_constraints[RS6000_CONSTRAINT_wH]"
"Altivec register to hold 32-bit integers or NO_REGS.")
......
gcc/config/rs6000/predicates.md
......@@ -406,13 +406,11 @@
return FP_REGNO_P (r);
})
;; Return true if this is a register that can has D-form addressing (GPR and
;; traditional FPR registers for scalars). ISA 3.0 (power9) adds D-form
;; addressing for scalars in Altivec registers.
;;
;; If this is a pseudo only allow for GPR fusion in power8. If we have the
;; power9 fusion allow the floating point types.
(define_predicate "toc_fusion_or_p9_reg_operand"
;; Return true if this is a register that can has D-form addressing (GPR,
;; traditional FPR registers, and Altivec registers for scalars). Unlike
;; power8 fusion, this fusion does not depend on putting the ADDIS instruction
;; into the GPR register being loaded.
(define_predicate "p9_fusion_reg_operand"
(match_code "reg,subreg")
{
HOST_WIDE_INT r;
......@@ -1664,35 +1662,6 @@
return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
})
;; Match the TOC memory operand that can be fused with an addis instruction.
;; This is used in matching a potential fused address before register
;; allocation.
(define_predicate "toc_fusion_mem_raw"
(match_code "mem")
{
if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
return false;
return small_toc_ref (XEXP (op, 0), Pmode);
})
;; Match the memory operand that has been fused with an addis instruction and
;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
(define_predicate "toc_fusion_mem_wrapped"
(match_code "mem")
{
rtx addr;
if (!TARGET_TOC_FUSION_INT)
return false;
if (!MEM_P (op))
return false;
addr = XEXP (op, 0);
return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
})
;; Match the first insn (addis) in fusing the combination of addis and loads to
;; GPR registers on power8.
(define_predicate "fusion_gpr_addis"
......
gcc/config/rs6000/rs6000-cpus.def
......@@ -135,7 +135,6 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
| OPTION_MASK_VSX)
#endif
......
gcc/config/rs6000/rs6000-protos.h
......@@ -97,7 +97,6 @@ extern void expand_fusion_p9_load (rtx *);
extern void expand_fusion_p9_store (rtx *);
extern const char *emit_fusion_p9_load (rtx, rtx, rtx);
extern const char *emit_fusion_p9_store (rtx, rtx, rtx);
extern rtx fusion_wrap_memory_address (rtx);
extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
enum reg_class);
extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
......
gcc/config/rs6000/rs6000.h
......@@ -699,19 +699,6 @@ extern int rs6000_vector_align[];
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
&& (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
/* Conditions to allow TOC fusion for loading/storing integers. */
#define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
&& TARGET_TOC_FUSION \
&& (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64)
/* Conditions to allow TOC fusion for loading/storing floating point. */
#define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
&& TARGET_TOC_FUSION \
&& (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64 \
&& TARGET_HARD_FLOAT)
/* Macro to say whether we can do optimizations where we need to do parts of
the calculation in 64-bit GPRs and then is transfered to the vector
registers. */
......
gcc/config/rs6000/rs6000.md
......@@ -137,7 +137,6 @@
UNSPEC_FUSION_GPR
UNSPEC_STACK_CHECK
UNSPEC_FUSION_P9
UNSPEC_FUSION_ADDIS
UNSPEC_ADD_ROUND_TO_ODD
UNSPEC_SUB_ROUND_TO_ODD
UNSPEC_MUL_ROUND_TO_ODD
......@@ -13621,66 +13620,11 @@
;; a GPR. The addis instruction must be adjacent to the load, and use the same
;; register that is being loaded. The fused ops must be physically adjacent.
;; There are two parts to addis fusion. The support for fused TOCs occur
;; before register allocation, and is meant to reduce the lifetime for the
;; tempoary register that holds the ADDIS result. On Power8 GPR loads, we try
;; to use the register that is being load. The peephole2 then gathers any
;; other fused possibilities that it can find after register allocation. If
;; power9 fusion is selected, we also fuse floating point loads/stores.
;; On Power8 GPR loads, we try to use the register that is being load. The
;; peephole2 then gathers any other fused possibilities that it can find after
;; register allocation. If power9 fusion is selected, we also fuse floating
;; point loads/stores.
;; Fused TOC support: Replace simple GPR loads with a fused form. This is done
;; before register allocation, so that we can avoid allocating a temporary base
;; register that won't be used, and that we try to load into base registers,
;; and not register 0. If we can't get a fused GPR load, generate a P9 fusion
;; (addis followed by load) even on power8.
(define_split
[(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand")
(match_operand:INT1 1 "toc_fusion_mem_raw"))]
"TARGET_TOC_FUSION_INT && can_create_pseudo_p ()"
[(parallel [(set (match_dup 0) (match_dup 2))
(unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
(use (match_dup 3))
(clobber (scratch:DI))])]
{
operands[2] = fusion_wrap_memory_address (operands[1]);
operands[3] = gen_rtx_REG (Pmode, TOC_REGISTER);
})
(define_insn "*toc_fusionload_<mode>"
[(set (match_operand:QHSI 0 "int_reg_operand" "=&b,??r")
(match_operand:QHSI 1 "toc_fusion_mem_wrapped" "wG,wG"))
(unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
(use (match_operand:DI 2 "base_reg_operand" "r,r"))
(clobber (match_scratch:DI 3 "=X,&b"))]
"TARGET_TOC_FUSION_INT"
{
if (base_reg_operand (operands[0], <MODE>mode))
return emit_fusion_gpr_load (operands[0], operands[1]);
return emit_fusion_p9_load (operands[0], operands[1], operands[3]);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn "*toc_fusionload_di"
[(set (match_operand:DI 0 "int_reg_operand" "=&b,??r,?d")
(match_operand:DI 1 "toc_fusion_mem_wrapped" "wG,wG,wG"))
(unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
(use (match_operand:DI 2 "base_reg_operand" "r,r,r"))
(clobber (match_scratch:DI 3 "=X,&b,&b"))]
"TARGET_TOC_FUSION_INT && TARGET_POWERPC64
&& (MEM_P (operands[1]) || int_reg_operand (operands[0], DImode))"
{
if (base_reg_operand (operands[0], DImode))
return emit_fusion_gpr_load (operands[0], operands[1]);
return emit_fusion_p9_load (operands[0], operands[1], operands[3]);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Find cases where the addis that feeds into a load instruction is either used
;; once or is the same as the target register, and replace it with the fusion
;; insn
......@@ -13702,7 +13646,7 @@
;; Fusion insn, created by the define_peephole2 above (and eventually by
;; reload)
(define_insn "fusion_gpr_load_<mode>"
(define_insn "*fusion_gpr_load_<mode>"
[(set (match_operand:INT1 0 "base_reg_operand" "=b")
(unspec:INT1 [(match_operand:INT1 1 "fusion_addis_mem_combo_load" "wF")]
UNSPEC_FUSION_GPR))]
......@@ -13719,7 +13663,7 @@
(define_peephole2
[(set (match_operand:P 0 "base_reg_operand")
(match_operand:P 1 "fusion_gpr_addis"))
(set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand")
(set (match_operand:SFDF 2 "p9_fusion_reg_operand")
(match_operand:SFDF 3 "fusion_offsettable_mem_operand"))]
"TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
&& fusion_p9_p (operands[0], operands[1], operands[2], operands[3])"
......@@ -13733,7 +13677,7 @@
[(set (match_operand:P 0 "base_reg_operand")
(match_operand:P 1 "fusion_gpr_addis"))
(set (match_operand:SFDF 2 "offsettable_mem_operand")
(match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))]
(match_operand:SFDF 3 "p9_fusion_reg_operand"))]
"TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
&& fusion_p9_p (operands[0], operands[1], operands[2], operands[3])
&& !rtx_equal_p (operands[0], operands[3])"
......@@ -13771,7 +13715,7 @@
;; reload). Because we want to eventually have secondary_reload generate
;; these, they have to have a single alternative that gives the register
;; classes. This means we need to have separate gpr/fpr/altivec versions.
(define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load"
(define_insn "*fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load"
[(set (match_operand:GPR_FUSION 0 "int_reg_operand" "=r")
(unspec:GPR_FUSION
[(match_operand:GPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")]
......@@ -13789,7 +13733,7 @@
[(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store"
(define_insn "*fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store"
[(set (match_operand:GPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF")
(unspec:GPR_FUSION
[(match_operand:GPR_FUSION 1 "int_reg_operand" "r")]
......@@ -13802,7 +13746,7 @@
[(set_attr "type" "store")
(set_attr "length" "8")])
(define_insn "fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load"
(define_insn "*fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load"
[(set (match_operand:FPR_FUSION 0 "vsx_register_operand" "=dwb")
(unspec:FPR_FUSION
[(match_operand:FPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")]
......@@ -13815,7 +13759,7 @@
[(set_attr "type" "fpload")
(set_attr "length" "8")])
(define_insn "fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store"
(define_insn "*fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store"
[(set (match_operand:FPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF")
(unspec:FPR_FUSION
[(match_operand:FPR_FUSION 1 "vsx_register_operand" "dwb")]
......
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