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Commit 0f686aa9 by James Greenhalgh Committed by James Greenhalgh
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[AArch64] [Neon types 4/10] Add type attributes to all simd insns 

gcc/

	* config/aarch64/iterators.md (Vetype): Add SF and DF modes.
	(fp): New.
	* config/aarch64/aarch64-simd.md (neon_type): Remove.
	* config/aarch64/aarch64-simd.md: Add "type" attribute to all
	patterns.

From-SVN: r203614
parent f7379e5e
Showing with 200 additions and 6 deletions
gcc/ChangeLog
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/iterators.md (Vetype): Add SF and DF modes.
(fp): New.
* config/aarch64/aarch64-simd.md (neon_type): Remove.
(aarch64_simd_dup<mode>): Add "type" attribute.
(aarch64_dup_lane<mode>): Likewise.
(aarch64_dup_lane_<vswap_width_name><mode>): Likewise.
(*aarch64_simd_mov<mode>): Likewise.
(aarch64_simd_mov_from_<mode>low): Likewise.
(aarch64_simd_mov_from_<mode>high): Likewise.
(orn<mode>3): Likewise.
(bic<mode>3): Likewise.
(add<mode>3): Likewise.
(sub<mode>3): Likewise.
(mul<mode>3): Likewise.
(*aarch64_mul3_elt<mode>): Likewise.
(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_128df): Likewise.
(*aarch64_mul3_elt_to_64v2df): Likewise.
(neg<mode>2): Likewise.
(abs<mode>2): Likewise.
(abd<mode>_3): Likewise.
(aba<mode>_3): Likewise.
(fabd<mode>_3): Likewise.
(*fabd_scalar<mode>3): Likewise.
(and<mode>3): Likewise.
(ior<mode>3): Likewise.
(xor<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(aarch64_simd_vec_set<mode>): Likewise.
(aarch64_simd_lshr<mode>): Likewise.
(aarch64_simd_ashr<mode>): Likewise.
(aarch64_simd_imm_shl<mode>): Likewise.
(aarch64_simd_reg_sshl<mode): Likewise.
(aarch64_simd_reg_shl<mode>_unsigned): Likewise.
(aarch64_simd_reg_shl<mode>_signed): Likewise.
(aarch64_simd_vec_setv2di): Likewise.
(aarch64_simd_vec_set<mode>): Likewise.
(aarch64_mla<mode>): Likewise.
(*aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mls<mode>): Likewise.
(*aarch64_mls_elt<mode>): Likewise.
(*aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(<su><maxmin><mode>3): Likewise.
(move_lo_quad_<mode>): Likewise.
(aarch64_simd_move_hi_quad_<mode>): Likewise.
(aarch64_simd_vec_pack_trunc_<mode>): Likewise.
(vec_pack_trunc_<mode>): Likewise.
(aarch64_simd_vec_unpack<su>_lo_<mode>): Likewise.
(aarch64_simd_vec_unpack<su>_hi_<mode>): Likewise.
(*aarch64_<su>mlal_lo<mode>): Likewise.
(*aarch64_<su>mlal_hi<mode>): Likewise.
(*aarch64_<su>mlsl_lo<mode>): Likewise.
(*aarch64_<su>mlsl_hi<mode>): Likewise.
(*aarch64_<su>mlal<mode>): Likewise.
(*aarch64_<su>mlsl<mode>): Likewise.
(aarch64_simd_vec_<su>mult_lo_<mode>): Likewise.
(aarch64_simd_vec_<su>mult_hi_<mode>): Likewise.
(add<mode>3): Likewise.
(sub<mode>3): Likewise.
(mul<mode>3): Likewise.
(div<mode>3): Likewise.
(neg<mode>2): Likewise.
(abs<mode>2): Likewise.
(fma<mode>4): Likewise.
(*aarch64_fma4_elt<mode>): Likewise.
(*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fma4_elt_to_128df): Likewise.
(*aarch64_fma4_elt_to_64v2df): Likewise.
(fnma<mode>4): Likewise.
(*aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>
(*aarch64_fnma4_elt_to_128df): Likewise.
(*aarch64_fnma4_elt_to_64v2df): Likewise.
(<frint_pattern><mode>2): Likewise.
(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): Likewise.
(<optab><fcvt_target><VDQF:VDQF:mode>2): Likewise.
(vec_unpacks_lo_v4sf): Likewise.
(aarch64_float_extend_lo_v2df): Likewise.
(vec_unpacks_hi_v4sf): Likewise.
(aarch64_float_truncate_lo_v2sf): Likewise.
(aarch64_float_truncate_hi_v4sf): Likewise.
(aarch64_vmls<mode>): Likewise.
(<su><maxmin><mode>3): Likewise.
(<maxmin_uns><mode>3): Likewise.
(reduc_<sur>plus_<mode>): Likewise.
(reduc_<sur>plus_v2di): Likewise.
(reduc_<sur>plus_v2si): Likewise.
(reduc_<sur>plus_<mode>): Likewise.
(aarch64_addpv4sf): Likewise.
(clz<mode>2): Likewise.
(reduc_<maxmin_uns>_<mode>): Likewise.
(reduc_<maxmin_uns>_v2di): Likewise.
(reduc_<maxmin_uns>_v2si): Likewise.
(reduc_<maxmin_uns>_<mode>): Likewise.
(reduc_<maxmin_uns>_v4sf): Likewise.
(aarch64_simd_bsl<mode>_internal): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>): Likewise.
(*aarch64_combinez<mode>): Likewise.
(aarch64_combine<mode>): Likewise.
(aarch64_simd_combine<mode>): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_hi_internal): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_lo_internal): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal): Likewise.
(aarch64_<sur>h<addsub><mode>): Likewise.
(aarch64_<sur><addsub>hn<mode>): Likewise.
(aarch64_<sur><addsub>hn2<mode>): Likewise.
(aarch64_pmul<mode>): Likewise.
(aarch64_<su_optab><optab><mode>): Likewise.
(aarch64_<sur>qadd<mode>): Likewise.
(aarch64_sqmovun<mode>): Likewise.
(aarch64_<sur>qmovn<mode>): Likewise.
(aarch64_s<optab><mode>): Likewise.
(aarch64_sq<r>dmulh<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>): Likewise.
(aarch64_sq<r>dmulh_laneq<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_n<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
(aarch64_sqdmull<mode>): Likewise.
(aarch64_sqdmull_lane<mode>_internal): Likewise.
(aarch64_sqdmull_n<mode>): Likewise.
(aarch64_sqdmull2<mode>_internal): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_n<mode>_internal): Likewise.
(aarch64_<sur>shl<mode>): Likewise.
(aarch64_<sur>q<r>shl<mode>
(aarch64_<sur>shll_n<mode>): Likewise.
(aarch64_<sur>shll2_n<mode>): Likewise.
(aarch64_<sur>shr_n<mode>): Likewise.
(aarch64_<sur>sra_n<mode>): Likewise.
(aarch64_<sur>s<lr>i_n<mode>): Likewise.
(aarch64_<sur>qshl<u>_n<mode>): Likewise.
(aarch64_<sur>q<r>shr<u>n_n<mode>): Likewise.
(aarch64_cm<optab><mode>): Likewise.
(aarch64_cm<optab>di): Likewise.
(aarch64_cm<optab><mode>): Likewise.
(aarch64_cm<optab>di): Likewise.
(aarch64_cmtst<mode>): Likewise.
(aarch64_cmtstdi): Likewise.
(aarch64_cm<optab><mode>): Likewise.
(*aarch64_fac<optab><mode>): Likewise.
(aarch64_addp<mode>): Likewise.
(aarch64_addpdi): Likewise.
(sqrt<mode>2): Likewise.
(vec_load_lanesoi<mode>): Likewise.
(vec_store_lanesoi<mode>): Likewise.
(vec_load_lanesci<mode>): Likewise.
(vec_store_lanesci<mode>): Likewise.
(vec_load_lanesxi<mode>): Likewise.
(vec_store_lanesxi<mode>): Likewise.
(*aarch64_mov<mode>): Likewise.
(aarch64_ld2<mode>_dreg): Likewise.
(aarch64_ld2<mode>_dreg): Likewise.
(aarch64_ld3<mode>_dreg): Likewise.
(aarch64_ld3<mode>_dreg): Likewise.
(aarch64_ld4<mode>_dreg): Likewise.
(aarch64_ld4<mode>_dreg): Likewise.
(aarch64_tbl1<mode>): Likewise.
(aarch64_tbl2v16qi): Likewise.
(aarch64_combinev16qi): Likewise.
(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): Likewise.
(aarch64_st2<mode>_dreg): Likewise.
(aarch64_st2<mode>_dreg): Likewise.
(aarch64_st3<mode>_dreg): Likewise.
(aarch64_st3<mode>_dreg): Likewise.
(aarch64_st4<mode>_dreg): Likewise.
(aarch64_st4<mode>_dreg): Likewise.
(*aarch64_simd_ld1r<mode>): Likewise.
(aarch64_frecpe<mode>): Likewise.
(aarch64_frecp<FRECP:frecp_suffix><mode>): Likewise.
(aarch64_frecps<mode>): Likewise.
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/iterators.md (V_elem_ch): New.
(q): Likewise.
(VQH_type): Likewise.
......
gcc/config/aarch64/iterators.md
......@@ -351,6 +351,7 @@
(V2SI "s") (V4SI "s")
(V2DI "d") (V2SF "s")
(V4SF "s") (V2DF "d")
(SF "s") (DF "d")
(QI "b") (HI "h")
(SI "s") (DI "d")])
......@@ -566,14 +567,23 @@
(V2SF "f") (V4SF "f")
(V2DF "f") (DF "f")])
;; Defined to '_fp' for types whose element type is a float type.
(define_mode_attr fp [(V8QI "") (V16QI "")
(V4HI "") (V8HI "")
(V2SI "") (V4SI "")
(DI "") (V2DI "")
(V2SF "_fp") (V4SF "_fp")
(V2DF "_fp") (DF "_fp")
(SF "_fp")])
;; Defined to '_q' for 128-bit types.
(define_mode_attr q [(V8QI "") (V16QI "_q")
(V4HI "") (V8HI "_q")
(V2SI "") (V4SI "_q")
(DI "") (V2DI "_q")
(V2SF "") (V4SF "_q")
(V2DF "_q")
(QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
(V4HI "") (V8HI "_q")
(V2SI "") (V4SI "_q")
(DI "") (V2DI "_q")
(V2SF "") (V4SF "_q")
(V2DF "_q")
(QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
;; -------------------------------------------------------------------
;; Code Iterators
......
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