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Commit 0f37323c by Richard Sandiford Committed by Richard Sandiford
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mips.h (ISA_HAS_WSBH): Define. 

gcc/
	* config/mips/mips.h (ISA_HAS_WSBH): Define.
	* config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New
	constants.
	(bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns.

gcc/testsuite/
	* gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c,
	gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c,
	gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests.

From-SVN: r203870
parent 4cd940de
Showing with 148 additions and 0 deletions
gcc/ChangeLog
2013-10-20 Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips.h (ISA_HAS_WSBH): Define.
* config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New
constants.
(bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns.
2013-10-19 John David Anglin <danglin@gcc.gnu.org>
PR target/58603
......
gcc/config/mips/mips.h
......@@ -972,6 +972,11 @@ struct mips_cpu_info {
|| TARGET_SMARTMIPS) \
&& !TARGET_MIPS16)
/* ISA has the WSBH (word swap bytes within halfwords) instruction.
64-bit targets also provide DSBH and DSHD. */
#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* ISA has data prefetch instructions. This controls use of 'pref'. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| TARGET_LOONGSON_2EF \
......
gcc/config/mips/mips.md
......@@ -74,6 +74,11 @@
UNSPEC_STORE_LEFT
UNSPEC_STORE_RIGHT
;; Integer operations that are too cumbersome to describe directly.
UNSPEC_WSBH
UNSPEC_DSBH
UNSPEC_DSHD
;; Floating-point moves.
UNSPEC_LOAD_LOW
UNSPEC_LOAD_HIGH
......@@ -5358,6 +5363,56 @@
}
[(set_attr "type" "shift")
(set_attr "mode" "<MODE>")])
(define_insn "bswaphi2"
[(set (match_operand:HI 0 "register_operand" "=d")
(bswap:HI (match_operand:HI 1 "register_operand" "d")))]
"ISA_HAS_WSBH"
"wsbh\t%0,%1"
[(set_attr "type" "shift")])
(define_insn_and_split "bswapsi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(bswap:SI (match_operand:SI 1 "register_operand" "d")))]
"ISA_HAS_WSBH && ISA_HAS_ROR"
"#"
""
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
(set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
""
[(set_attr "insn_count" "2")])
(define_insn_and_split "bswapdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(bswap:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && ISA_HAS_WSBH"
"#"
""
[(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))
(set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]
""
[(set_attr "insn_count" "2")])
(define_insn "wsbh"
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]
"ISA_HAS_WSBH"
"wsbh\t%0,%1"
[(set_attr "type" "shift")])
(define_insn "dsbh"
[(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]
"TARGET_64BIT && ISA_HAS_WSBH"
"dsbh\t%0,%1"
[(set_attr "type" "shift")])
(define_insn "dshd"
[(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]
"TARGET_64BIT && ISA_HAS_WSBH"
"dshd\t%0,%1"
[(set_attr "type" "shift")])
;;
;; ....................
......
gcc/testsuite/ChangeLog
2013-10-20 Richard Sandiford <rdsandiford@googlemail.com>
* gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c,
gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c,
gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests.
2013-10-19 John David Anglin <danglin@gcc.gnu.org>
* c-c++-common/opaque-vector.c: Skip long double test on hppa.
......
gcc/testsuite/gcc.target/mips/bswap-1.c 0 → 100644
/* { dg-options "isa_rev>=2" } */
/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
NOMIPS16 unsigned short
foo (unsigned short x)
{
return ((x << 8) & 0xff00) | ((x >> 8) & 0xff);
}
/* { dg-final { scan-assembler "\twsbh\t" } } */
gcc/testsuite/gcc.target/mips/bswap-2.c 0 → 100644
/* { dg-options "isa_rev>=2" } */
NOMIPS16 unsigned short
foo (unsigned short x)
{
return __builtin_bswap16 (x);
}
/* { dg-final { scan-assembler "\twsbh\t" } } */
gcc/testsuite/gcc.target/mips/bswap-3.c 0 → 100644
/* { dg-options "isa_rev>=2" } */
/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
NOMIPS16 unsigned int
foo (unsigned int x)
{
return (((x << 24) & 0xff000000)
| ((x << 8) & 0xff0000)
| ((x >> 8) & 0xff00)
| ((x >> 24) & 0xff));
}
/* { dg-final { scan-assembler "\twsbh\t" } } */
/* { dg-final { scan-assembler "\tror\t" } } */
gcc/testsuite/gcc.target/mips/bswap-4.c 0 → 100644
/* { dg-options "isa_rev>=2" } */
NOMIPS16 unsigned int
foo (unsigned int x)
{
return __builtin_bswap32 (x);
}
/* { dg-final { scan-assembler "\twsbh\t" } } */
/* { dg-final { scan-assembler "\tror\t" } } */
gcc/testsuite/gcc.target/mips/bswap-5.c 0 → 100644
/* { dg-options "isa_rev>=2 -mgp64" } */
/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
typedef unsigned long long uint64_t;
NOMIPS16 uint64_t
foo (uint64_t x)
{
return (((x << 56) & 0xff00000000000000ull)
| ((x << 40) & 0xff000000000000ull)
| ((x << 24) & 0xff0000000000ull)
| ((x << 8) & 0xff00000000ull)
| ((x >> 8) & 0xff000000)
| ((x >> 24) & 0xff0000)
| ((x >> 40) & 0xff00)
| ((x >> 56) & 0xff));
}
/* { dg-final { scan-assembler "\tdsbh\t" } } */
/* { dg-final { scan-assembler "\tdshd\t" } } */
gcc/testsuite/gcc.target/mips/bswap-6.c 0 → 100644
/* { dg-options "isa_rev>=2 -mgp64" } */
typedef unsigned long long uint64_t;
NOMIPS16 uint64_t
foo (uint64_t x)
{
return __builtin_bswap64 (x);
}
/* { dg-final { scan-assembler "\tdsbh\t" } } */
/* { dg-final { scan-assembler "\tdshd\t" } } */
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