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Commit 0efbf084 by David Edelsohn
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[multiple changes] 

2012-09-19  Tulio Magno Quites Machado Filho  <tuliom@linux.vnet.ibm.com>

        * config/rs6000/rs6000-builtin.def: Add __builtin_ppc_get_timebase
        and __builtin_ppc_mftb.
        * config/rs6000/rs6000.c (rs6000_expand_zeroop_builtin): New
        function to expand an expression that calls a built-in without
        arguments.
        (rs6000_expand_builtin): Add __builtin_ppc_get_timebase and
        __builtin_ppc_mftb.
        (rs6000_init_builtins): Likewise.
        * config/rs6000/rs6000.md (rs6000_get_timebase): New pattern.
        (rs6000_get_timebase_ppc32): New pattern.
        (rs6000_mftb_<mode>): New pattern.

        * doc/extend.texi (PowerPC Built-in Functions): New section.
        (PowerPC AltiVec/VSX Built-in Functions):
        Move some built-ins unrelated to Altivec/VSX to the new section.

2012-09-19  David Edelsohn  <dje.gcc@gmail.com>

        * rs6000.md (mac*): Remove extra spaces.
        (mulhw*): Same.

From-SVN: r191491
parent 4eddc42b
Showing with 207 additions and 51 deletions
gcc/ChangeLog
2012-09-19 Tulio Magno Quites Machado Filho <tuliom@linux.vnet.ibm.com>
* config/rs6000/rs6000-builtin.def: Add __builtin_ppc_get_timebase
and __builtin_ppc_mftb.
* config/rs6000/rs6000.c (rs6000_expand_zeroop_builtin): New
function to expand an expression that calls a built-in without
arguments.
(rs6000_expand_builtin): Add __builtin_ppc_get_timebase and
__builtin_ppc_mftb.
(rs6000_init_builtins): Likewise.
* config/rs6000/rs6000.md (rs6000_get_timebase): New pattern.
(rs6000_get_timebase_ppc32): New pattern.
(rs6000_mftb_<mode>): New pattern.
* doc/extend.texi (PowerPC Built-in Functions): New section.
(PowerPC AltiVec/VSX Built-in Functions):
Move some built-ins unrelated to Altivec/VSX to the new section.
2012-09-19 David Edelsohn <dje.gcc@gmail.com>
* rs6000.md (mac*): Remove extra spaces.
(mulhw*): Same.
2012-09-19 Oleg Endo <olegendo@gcc.gnu.org> 2012-09-19 Oleg Endo <olegendo@gcc.gnu.org>
PR target/54089 PR target/54089
......
gcc/config/rs6000/rs6000-builtin.def
...@@ -1429,6 +1429,12 @@ BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE, ...@@ -1429,6 +1429,12 @@ BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE,
BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES,
RS6000_BTC_FP) RS6000_BTC_FP)
BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase",
RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb",
RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
/* Darwin CfString builtin. */ /* Darwin CfString builtin. */
BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
RS6000_BTC_MISC) RS6000_BTC_MISC)
gcc/config/rs6000/rs6000.c
...@@ -9748,6 +9748,30 @@ rs6000_overloaded_builtin_p (enum rs6000_builtins fncode) ...@@ -9748,6 +9748,30 @@ rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0; return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
} }
/* Expand an expression EXP that calls a builtin without arguments. */
static rtx
rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
{
rtx pat;
enum machine_mode tmode = insn_data[icode].operand[0].mode;
if (icode == CODE_FOR_nothing)
/* Builtin not supported on this processor. */
return 0;
if (target == 0
|| GET_MODE (target) != tmode
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
pat = GEN_FCN (icode) (target);
if (! pat)
return 0;
emit_insn (pat);
return target;
}
static rtx static rtx
rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target) rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
...@@ -11337,6 +11361,16 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, ...@@ -11337,6 +11361,16 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
? CODE_FOR_bpermd_di ? CODE_FOR_bpermd_di
: CODE_FOR_bpermd_si), exp, target); : CODE_FOR_bpermd_si), exp, target);
case RS6000_BUILTIN_GET_TB:
return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
target);
case RS6000_BUILTIN_MFTB:
return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
? CODE_FOR_rs6000_mftb_di
: CODE_FOR_rs6000_mftb_si),
target);
case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
case ALTIVEC_BUILTIN_MASK_FOR_STORE: case ALTIVEC_BUILTIN_MASK_FOR_STORE:
{ {
...@@ -11621,6 +11655,18 @@ rs6000_init_builtins (void) ...@@ -11621,6 +11655,18 @@ rs6000_init_builtins (void)
POWER7_BUILTIN_BPERMD, "__builtin_bpermd"); POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD); def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
ftype = build_function_type_list (unsigned_intDI_type_node,
NULL_TREE);
def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
if (TARGET_64BIT)
ftype = build_function_type_list (unsigned_intDI_type_node,
NULL_TREE);
else
ftype = build_function_type_list (unsigned_intSI_type_node,
NULL_TREE);
def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
#if TARGET_XCOFF #if TARGET_XCOFF
/* AIX libm provides clog as __clog. */ /* AIX libm provides clog as __clog. */
if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE) if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
......
gcc/config/rs6000/rs6000.md
...@@ -136,6 +136,7 @@ ...@@ -136,6 +136,7 @@
UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
UNSPECV_EH_RR ; eh_reg_restore UNSPECV_EH_RR ; eh_reg_restore
UNSPECV_ISYNC ; isync instruction UNSPECV_ISYNC ; isync instruction
UNSPECV_MFTB ; move from time base
]) ])
...@@ -991,7 +992,7 @@ ...@@ -991,7 +992,7 @@
(match_dup 1))) (match_dup 1)))
(match_dup 4)))] (match_dup 4)))]
"TARGET_MULHW" "TARGET_MULHW"
"macchw. %0, %1, %2" "macchw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*macchw" (define_insn "*macchw"
...@@ -1003,7 +1004,7 @@ ...@@ -1003,7 +1004,7 @@
(match_operand:HI 1 "gpc_reg_operand" "r"))) (match_operand:HI 1 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))] (match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW" "TARGET_MULHW"
"macchw %0, %1, %2" "macchw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*macchwuc" (define_insn "*macchwuc"
...@@ -1023,7 +1024,7 @@ ...@@ -1023,7 +1024,7 @@
(match_dup 1))) (match_dup 1)))
(match_dup 4)))] (match_dup 4)))]
"TARGET_MULHW" "TARGET_MULHW"
"macchwu. %0, %1, %2" "macchwu. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*macchwu" (define_insn "*macchwu"
...@@ -1035,7 +1036,7 @@ ...@@ -1035,7 +1036,7 @@
(match_operand:HI 1 "gpc_reg_operand" "r"))) (match_operand:HI 1 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))] (match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW" "TARGET_MULHW"
"macchwu %0, %1, %2" "macchwu %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*machhwc" (define_insn "*machhwc"
...@@ -1057,7 +1058,7 @@ ...@@ -1057,7 +1058,7 @@
(const_int 16))) (const_int 16)))
(match_dup 4)))] (match_dup 4)))]
"TARGET_MULHW" "TARGET_MULHW"
"machhw. %0, %1, %2" "machhw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*machhw" (define_insn "*machhw"
...@@ -1070,7 +1071,7 @@ ...@@ -1070,7 +1071,7 @@
(const_int 16))) (const_int 16)))
(match_operand:SI 3 "gpc_reg_operand" "0")))] (match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW" "TARGET_MULHW"
"machhw %0, %1, %2" "machhw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*machhwuc" (define_insn "*machhwuc"
...@@ -1092,7 +1093,7 @@ ...@@ -1092,7 +1093,7 @@
(const_int 16))) (const_int 16)))
(match_dup 4)))] (match_dup 4)))]
"TARGET_MULHW" "TARGET_MULHW"
"machhwu. %0, %1, %2" "machhwu. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*machhwu" (define_insn "*machhwu"
...@@ -1105,7 +1106,7 @@ ...@@ -1105,7 +1106,7 @@
(const_int 16))) (const_int 16)))
(match_operand:SI 3 "gpc_reg_operand" "0")))] (match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW" "TARGET_MULHW"
"machhwu %0, %1, %2" "machhwu %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*maclhwc" (define_insn "*maclhwc"
...@@ -1123,7 +1124,7 @@ ...@@ -1123,7 +1124,7 @@
(match_dup 2))) (match_dup 2)))
(match_dup 4)))] (match_dup 4)))]
"TARGET_MULHW" "TARGET_MULHW"
"maclhw. %0, %1, %2" "maclhw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*maclhw" (define_insn "*maclhw"
...@@ -1134,7 +1135,7 @@ ...@@ -1134,7 +1135,7 @@
(match_operand:HI 2 "gpc_reg_operand" "r"))) (match_operand:HI 2 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))] (match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW" "TARGET_MULHW"
"maclhw %0, %1, %2" "maclhw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*maclhwuc" (define_insn "*maclhwuc"
...@@ -1152,7 +1153,7 @@ ...@@ -1152,7 +1153,7 @@
(match_dup 2))) (match_dup 2)))
(match_dup 4)))] (match_dup 4)))]
"TARGET_MULHW" "TARGET_MULHW"
"maclhwu. %0, %1, %2" "maclhwu. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*maclhwu" (define_insn "*maclhwu"
...@@ -1163,7 +1164,7 @@ ...@@ -1163,7 +1164,7 @@
(match_operand:HI 2 "gpc_reg_operand" "r"))) (match_operand:HI 2 "gpc_reg_operand" "r")))
(match_operand:SI 3 "gpc_reg_operand" "0")))] (match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW" "TARGET_MULHW"
"maclhwu %0, %1, %2" "maclhwu %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*nmacchwc" (define_insn "*nmacchwc"
...@@ -1183,7 +1184,7 @@ ...@@ -1183,7 +1184,7 @@
(sign_extend:SI (sign_extend:SI
(match_dup 1)))))] (match_dup 1)))))]
"TARGET_MULHW" "TARGET_MULHW"
"nmacchw. %0, %1, %2" "nmacchw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*nmacchw" (define_insn "*nmacchw"
...@@ -1195,7 +1196,7 @@ ...@@ -1195,7 +1196,7 @@
(sign_extend:SI (sign_extend:SI
(match_operand:HI 1 "gpc_reg_operand" "r")))))] (match_operand:HI 1 "gpc_reg_operand" "r")))))]
"TARGET_MULHW" "TARGET_MULHW"
"nmacchw %0, %1, %2" "nmacchw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*nmachhwc" (define_insn "*nmachhwc"
...@@ -1217,7 +1218,7 @@ ...@@ -1217,7 +1218,7 @@
(match_dup 2) (match_dup 2)
(const_int 16)))))] (const_int 16)))))]
"TARGET_MULHW" "TARGET_MULHW"
"nmachhw. %0, %1, %2" "nmachhw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*nmachhw" (define_insn "*nmachhw"
...@@ -1230,7 +1231,7 @@ ...@@ -1230,7 +1231,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 16)))))] (const_int 16)))))]
"TARGET_MULHW" "TARGET_MULHW"
"nmachhw %0, %1, %2" "nmachhw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*nmaclhwc" (define_insn "*nmaclhwc"
...@@ -1248,7 +1249,7 @@ ...@@ -1248,7 +1249,7 @@
(sign_extend:SI (sign_extend:SI
(match_dup 2)))))] (match_dup 2)))))]
"TARGET_MULHW" "TARGET_MULHW"
"nmaclhw. %0, %1, %2" "nmaclhw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*nmaclhw" (define_insn "*nmaclhw"
...@@ -1259,7 +1260,7 @@ ...@@ -1259,7 +1260,7 @@
(sign_extend:SI (sign_extend:SI
(match_operand:HI 2 "gpc_reg_operand" "r")))))] (match_operand:HI 2 "gpc_reg_operand" "r")))))]
"TARGET_MULHW" "TARGET_MULHW"
"nmaclhw %0, %1, %2" "nmaclhw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulchwc" (define_insn "*mulchwc"
...@@ -1277,7 +1278,7 @@ ...@@ -1277,7 +1278,7 @@
(sign_extend:SI (sign_extend:SI
(match_dup 1))))] (match_dup 1))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulchw. %0, %1, %2" "mulchw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulchw" (define_insn "*mulchw"
...@@ -1288,7 +1289,7 @@ ...@@ -1288,7 +1289,7 @@
(sign_extend:SI (sign_extend:SI
(match_operand:HI 1 "gpc_reg_operand" "r"))))] (match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulchw %0, %1, %2" "mulchw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulchwuc" (define_insn "*mulchwuc"
...@@ -1306,7 +1307,7 @@ ...@@ -1306,7 +1307,7 @@
(zero_extend:SI (zero_extend:SI
(match_dup 1))))] (match_dup 1))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulchwu. %0, %1, %2" "mulchwu. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulchwu" (define_insn "*mulchwu"
...@@ -1317,7 +1318,7 @@ ...@@ -1317,7 +1318,7 @@
(zero_extend:SI (zero_extend:SI
(match_operand:HI 1 "gpc_reg_operand" "r"))))] (match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulchwu %0, %1, %2" "mulchwu %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulhhwc" (define_insn "*mulhhwc"
...@@ -1337,7 +1338,7 @@ ...@@ -1337,7 +1338,7 @@
(match_dup 2) (match_dup 2)
(const_int 16))))] (const_int 16))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulhhw. %0, %1, %2" "mulhhw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulhhw" (define_insn "*mulhhw"
...@@ -1349,7 +1350,7 @@ ...@@ -1349,7 +1350,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 16))))] (const_int 16))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulhhw %0, %1, %2" "mulhhw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulhhwuc" (define_insn "*mulhhwuc"
...@@ -1369,7 +1370,7 @@ ...@@ -1369,7 +1370,7 @@
(match_dup 2) (match_dup 2)
(const_int 16))))] (const_int 16))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulhhwu. %0, %1, %2" "mulhhwu. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mulhhwu" (define_insn "*mulhhwu"
...@@ -1381,7 +1382,7 @@ ...@@ -1381,7 +1382,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 16))))] (const_int 16))))]
"TARGET_MULHW" "TARGET_MULHW"
"mulhhwu %0, %1, %2" "mulhhwu %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mullhwc" (define_insn "*mullhwc"
...@@ -1397,7 +1398,7 @@ ...@@ -1397,7 +1398,7 @@
(sign_extend:SI (sign_extend:SI
(match_dup 2))))] (match_dup 2))))]
"TARGET_MULHW" "TARGET_MULHW"
"mullhw. %0, %1, %2" "mullhw. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mullhw" (define_insn "*mullhw"
...@@ -1407,7 +1408,7 @@ ...@@ -1407,7 +1408,7 @@
(sign_extend:SI (sign_extend:SI
(match_operand:HI 2 "gpc_reg_operand" "r"))))] (match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW" "TARGET_MULHW"
"mullhw %0, %1, %2" "mullhw %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mullhwuc" (define_insn "*mullhwuc"
...@@ -1423,7 +1424,7 @@ ...@@ -1423,7 +1424,7 @@
(zero_extend:SI (zero_extend:SI
(match_dup 2))))] (match_dup 2))))]
"TARGET_MULHW" "TARGET_MULHW"
"mullhwu. %0, %1, %2" "mullhwu. %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
(define_insn "*mullhwu" (define_insn "*mullhwu"
...@@ -1433,7 +1434,7 @@ ...@@ -1433,7 +1434,7 @@
(zero_extend:SI (zero_extend:SI
(match_operand:HI 2 "gpc_reg_operand" "r"))))] (match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW" "TARGET_MULHW"
"mullhwu %0, %1, %2" "mullhwu %0,%1,%2"
[(set_attr "type" "imul3")]) [(set_attr "type" "imul3")])
;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support. ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
...@@ -1447,7 +1448,7 @@ ...@@ -1447,7 +1448,7 @@
(match_dup 2)] (match_dup 2)]
UNSPEC_DLMZB))] UNSPEC_DLMZB))]
"TARGET_DLMZB" "TARGET_DLMZB"
"dlmzb. %0, %1, %2") "dlmzb. %0,%1,%2")
(define_expand "strlensi" (define_expand "strlensi"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
...@@ -7707,8 +7708,8 @@ ...@@ -7707,8 +7708,8 @@
mt%0 %1 mt%0 %1
mt%0 %1 mt%0 %1
nop nop
stfs%U0%X0 %1, %0 stfs%U0%X0 %1,%0
lfs%U1%X1 %0, %1" lfs%U1%X1 %0,%1"
[(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*") [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
...@@ -13873,6 +13874,71 @@ ...@@ -13873,6 +13874,71 @@
"" ""
"") "")
(define_expand "rs6000_get_timebase"
[(use (match_operand:DI 0 "gpc_reg_operand" ""))]
""
{
if (TARGET_POWERPC64)
emit_insn (gen_rs6000_mftb_di (operands[0]));
else
emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
DONE;
})
(define_insn "rs6000_get_timebase_ppc32"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
(clobber (match_scratch:SI 1 "=r"))
(clobber (match_scratch:CC 2 "=y"))]
"!TARGET_POWERPC64"
{
if (WORDS_BIG_ENDIAN)
if (TARGET_MFCRF)
{
return "mfspr %0,269\;"
"mfspr %L0,268\;"
"mfspr %1,269\;"
"cmpw %2,%0,%1\;"
"bne- %2,$-16";
}
else
{
return "mftbu %0\;"
"mftb %L0\;"
"mftbu %1\;"
"cmpw %2,%0,%1\;"
"bne- %2,$-16";
}
else
if (TARGET_MFCRF)
{
return "mfspr %L0,269\;"
"mfspr %0,268\;"
"mfspr %1,269\;"
"cmpw %2,%L0,%1\;"
"bne- %2,$-16";
}
else
{
return "mftbu %L0\;"
"mftb %0\;"
"mftbu %1\;"
"cmpw %2,%L0,%1\;"
"bne- %2,$-16";
}
})
(define_insn "rs6000_mftb_<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
""
{
if (TARGET_MFCRF)
return "mfspr %0,268";
else
return "mftb %0";
})
(include "sync.md") (include "sync.md")
......
gcc/doc/extend.texi
...@@ -8647,6 +8647,7 @@ instructions, but allow the compiler to schedule those calls. ...@@ -8647,6 +8647,7 @@ instructions, but allow the compiler to schedule those calls.
* MIPS Loongson Built-in Functions:: * MIPS Loongson Built-in Functions::
* Other MIPS Built-in Functions:: * Other MIPS Built-in Functions::
* picoChip Built-in Functions:: * picoChip Built-in Functions::
* PowerPC Built-in Functions::
* PowerPC AltiVec/VSX Built-in Functions:: * PowerPC AltiVec/VSX Built-in Functions::
* RX Built-in Functions:: * RX Built-in Functions::
* SPARC VIS Built-in Functions:: * SPARC VIS Built-in Functions::
...@@ -11596,6 +11597,38 @@ GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE} ...@@ -11596,6 +11597,38 @@ GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE}
when this function is available. when this function is available.
@end table @end table
@node PowerPC Built-in Functions
@subsection PowerPC Built-in Functions
These built-in functions are available for the PowerPC family of
processors:
@smallexample
float __builtin_recipdivf (float, float);
float __builtin_rsqrtf (float);
double __builtin_recipdiv (double, double);
double __builtin_rsqrt (double);
long __builtin_bpermd (long, long);
uint64_t __builtin_ppc_get_timebase ();
unsigned long __builtin_ppc_mftb ();
@end smallexample
The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and
@code{__builtin_rsqrtf} functions generate multiple instructions to
implement the reciprocal sqrt functionality using reciprocal sqrt
estimate instructions.
The @code{__builtin_recipdiv}, and @code{__builtin_recipdivf}
functions generate multiple instructions to implement division using
the reciprocal estimate instructions.
The @code{__builtin_ppc_get_timebase} and @code{__builtin_ppc_mftb}
functions generate instructions to read the Time Base Register. The
@code{__builtin_ppc_get_timebase} function may generate multiple
instructions and always returns the 64 bits of the Time Base Register.
The @code{__builtin_ppc_mftb} function always generates one instruction and
returns the Time Base Register value as an unsigned long, throwing away
the most significant word on 32-bit environments.
@node PowerPC AltiVec/VSX Built-in Functions @node PowerPC AltiVec/VSX Built-in Functions
@subsection PowerPC AltiVec Built-in Functions @subsection PowerPC AltiVec Built-in Functions
...@@ -13653,24 +13686,6 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and ...@@ -13653,24 +13686,6 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and
@samp{vec_vsx_st} builtins will always generate the VSX @samp{LXVD2X}, @samp{vec_vsx_st} builtins will always generate the VSX @samp{LXVD2X},
@samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
GCC provides a few other builtins on Powerpc to access certain instructions:
@smallexample
float __builtin_recipdivf (float, float);
float __builtin_rsqrtf (float);
double __builtin_recipdiv (double, double);
double __builtin_rsqrt (double);
long __builtin_bpermd (long, long);
@end smallexample
The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and
@code{__builtin_rsqrtf} functions generate multiple instructions to
implement the reciprocal sqrt functionality using reciprocal sqrt
estimate instructions.
The @code{__builtin_recipdiv}, and @code{__builtin_recipdivf}
functions generate multiple instructions to implement division using
the reciprocal estimate instructions.
@node RX Built-in Functions @node RX Built-in Functions
@subsection RX Built-in Functions @subsection RX Built-in Functions
GCC supports some of the RX instructions which cannot be expressed in GCC supports some of the RX instructions which cannot be expressed in
......
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