h8300.c (output_simode_bld): Clear the destination first if possible.

	* config/h8300/h8300.c (output_simode_bld): Clear the
	destination first if possible.
	* config/h8300/h8300.md (extzv_1_r_h8300hs): Add an
	alternative.
	(extzv_1_r_inv_h8300hs): Likewise.

From-SVN: r63867

gcc/ChangeLog

+2003-03-05  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* config/h8300/h8300.c (output_simode_bld): Clear the
+	destination first if possible.
+	* config/h8300/h8300.md (extzv_1_r_h8300hs): Add an
+	alternative.
+	(extzv_1_r_inv_h8300hs): Likewise.
+
 2003-03-05  Zdenek Dvorak  <rakdver@atrey.karlin.mff.cuni.cz>
 
 	* basic-block.h (EDGE_IRREDUCIBLE_LOOP, EDGE_ALL_FLAGS): New.

gcc/config/h8300/h8300.c

@@ -4112,14 +4112,24 @@ output_simode_bld (bild, operands)
     }
   else
     {
+      /* Determine if we can clear the destination first.  */
+      int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
+			 && REGNO (operands[0]) != REGNO (operands[1]));
+
+      if (clear_first)
+	output_asm_insn ("sub.l\t%S0,%S0", operands);
+
       /* Output the bit load or bit inverse load.  */
       if (bild)
 	output_asm_insn ("bild\t%Z2,%Y1", operands);
       else
 	output_asm_insn ("bld\t%Z2,%Y1", operands);
 
-      /* Clear the destination register and perform the bit store.  */
-      output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
+      if (!clear_first)
+	output_asm_insn ("xor.l\t%S0,%S0", operands);
+
+      /* Perform the bit store.  */
+      output_asm_insn ("bst\t#0,%w0", operands);
     }
 
   /* All done.  */

gcc/config/h8300/h8300.md

@@ -2503,15 +2503,15 @@
    (set_attr "length" "8")])
 
 (define_insn "*extzv_1_r_h8300hs"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
 			 (const_int 1)
-			 (match_operand 2 "const_int_operand" "n")))]
+			 (match_operand 2 "const_int_operand" "n,n")))]
   "(TARGET_H8300H || TARGET_H8300S)
    && INTVAL (operands[2]) < 16"
   "* return output_simode_bld (0, operands);"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
+  [(set_attr "cc" "clobber,clobber")
+   (set_attr "length" "8,6")])
 
 ;;
 ;; Inverted loads with a 32bit destination.
@@ -2531,17 +2531,17 @@
    (set_attr "length" "8")])
 
 (define_insn "*extzv_1_r_inv_h8300hs"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
-				 (match_operand 3 "const_int_operand" "n"))
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
+				 (match_operand 3 "const_int_operand" "n,n"))
 			 (const_int 1)
-			 (match_operand 2 "const_int_operand" "n")))]
+			 (match_operand 2 "const_int_operand" "n,n")))]
   "(TARGET_H8300H || TARGET_H8300S)
    && INTVAL (operands[2]) < 16
    && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
   "* return output_simode_bld (1, operands);"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
+  [(set_attr "cc" "clobber,clobber")
+   (set_attr "length" "8,6")])
 
 (define_expand "insv"
   [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")