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riscv-gcc-1
Commit 0e26bf3d by Kyrylo Tkachov Committed by Kyrylo Tkachov
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arm-ldmstm.ml: Set "predicable_short_it" to "no" where appropriate. 

2013-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no"
	where appropriate.
	* config/arm/ldmstm.md: Regenerate.

From-SVN: r199734
parent 12b4e7ef
Showing with 60 additions and 25 deletions
gcc/ChangeLog
2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no"
where appropriate.
* config/arm/ldmstm.md: Regenerate.
2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/sync.md (atomic_loaddi_1): * config/arm/sync.md (atomic_loaddi_1):
Disable predication for arm_restrict_it. Disable predication for arm_restrict_it.
(arm_load_exclusive<mode>): Likewise. (arm_load_exclusive<mode>): Likewise.
......
gcc/config/arm/arm-ldmstm.ml
...@@ -146,12 +146,15 @@ let can_thumb addrmode update is_store = ...@@ -146,12 +146,15 @@ let can_thumb addrmode update is_store =
| IA, true, true -> true | IA, true, true -> true
| _ -> false | _ -> false
exception InvalidAddrMode of string;;
let target addrmode thumb = let target addrmode thumb =
match addrmode, thumb with match addrmode, thumb with
IA, true -> "TARGET_THUMB1" IA, true -> "TARGET_THUMB1"
| IA, false -> "TARGET_32BIT" | IA, false -> "TARGET_32BIT"
| DB, false -> "TARGET_32BIT" | DB, false -> "TARGET_32BIT"
| _, false -> "TARGET_ARM" | _, false -> "TARGET_ARM"
| _, _ -> raise (InvalidAddrMode "ERROR: Invalid Addressing mode for Thumb1.")
let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = let write_pattern_1 name ls addrmode nregs write_set_fn update thumb =
let astr = string_of_addrmode addrmode in let astr = string_of_addrmode addrmode in
...@@ -181,8 +184,10 @@ let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = ...@@ -181,8 +184,10 @@ let write_pattern_1 name ls addrmode nregs write_set_fn update thumb =
done; done;
Printf.printf "}\"\n"; Printf.printf "}\"\n";
Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs;
begin if not thumb then if not thumb then begin
Printf.printf "\n (set_attr \"predicable\" \"yes\")"; Printf.printf "\n (set_attr \"predicable\" \"yes\")";
if addrmode == IA || addrmode == DB then
Printf.printf "\n (set_attr \"predicable_short_it\" \"no\")";
end; end;
Printf.printf "])\n\n" Printf.printf "])\n\n"
......
gcc/config/arm/ldmstm.md
...@@ -37,7 +37,8 @@ ...@@ -37,7 +37,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%(ia%)\t%5, {%1, %2, %3, %4}" "ldm%(ia%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load4") [(set_attr "type" "load4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_ldm4_ia" (define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -74,7 +75,8 @@ ...@@ -74,7 +75,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldm%(ia%)\t%5!, {%1, %2, %3, %4}" "ldm%(ia%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load4") [(set_attr "type" "load4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_ldm4_ia_update" (define_insn "*thumb_ldm4_ia_update"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -108,7 +110,8 @@ ...@@ -108,7 +110,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(ia%)\t%5, {%1, %2, %3, %4}" "stm%(ia%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm4_ia_update" (define_insn "*stm4_ia_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -125,7 +128,8 @@ ...@@ -125,7 +128,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stm%(ia%)\t%5!, {%1, %2, %3, %4}" "stm%(ia%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_stm4_ia_update" (define_insn "*thumb_stm4_ia_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -302,7 +306,8 @@ ...@@ -302,7 +306,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%(db%)\t%5, {%1, %2, %3, %4}" "ldm%(db%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load4") [(set_attr "type" "load4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*ldm4_db_update" (define_insn "*ldm4_db_update"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -323,7 +328,8 @@ ...@@ -323,7 +328,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldm%(db%)\t%5!, {%1, %2, %3, %4}" "ldm%(db%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load4") [(set_attr "type" "load4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm4_db" (define_insn "*stm4_db"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -338,7 +344,8 @@ ...@@ -338,7 +344,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(db%)\t%5, {%1, %2, %3, %4}" "stm%(db%)\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm4_db_update" (define_insn "*stm4_db_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -355,7 +362,8 @@ ...@@ -355,7 +362,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stm%(db%)\t%5!, {%1, %2, %3, %4}" "stm%(db%)\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store4") [(set_attr "type" "store4")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
...@@ -477,7 +485,8 @@ ...@@ -477,7 +485,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%(ia%)\t%4, {%1, %2, %3}" "ldm%(ia%)\t%4, {%1, %2, %3}"
[(set_attr "type" "load3") [(set_attr "type" "load3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_ldm3_ia" (define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -508,7 +517,8 @@ ...@@ -508,7 +517,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%(ia%)\t%4!, {%1, %2, %3}" "ldm%(ia%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "load3") [(set_attr "type" "load3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_ldm3_ia_update" (define_insn "*thumb_ldm3_ia_update"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -537,7 +547,8 @@ ...@@ -537,7 +547,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(ia%)\t%4, {%1, %2, %3}" "stm%(ia%)\t%4, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm3_ia_update" (define_insn "*stm3_ia_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -552,7 +563,8 @@ ...@@ -552,7 +563,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(ia%)\t%4!, {%1, %2, %3}" "stm%(ia%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_stm3_ia_update" (define_insn "*thumb_stm3_ia_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -704,7 +716,8 @@ ...@@ -704,7 +716,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%(db%)\t%4, {%1, %2, %3}" "ldm%(db%)\t%4, {%1, %2, %3}"
[(set_attr "type" "load3") [(set_attr "type" "load3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*ldm3_db_update" (define_insn "*ldm3_db_update"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -722,7 +735,8 @@ ...@@ -722,7 +735,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%(db%)\t%4!, {%1, %2, %3}" "ldm%(db%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "load3") [(set_attr "type" "load3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm3_db" (define_insn "*stm3_db"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -735,7 +749,8 @@ ...@@ -735,7 +749,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(db%)\t%4, {%1, %2, %3}" "stm%(db%)\t%4, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm3_db_update" (define_insn "*stm3_db_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -750,7 +765,8 @@ ...@@ -750,7 +765,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%(db%)\t%4!, {%1, %2, %3}" "stm%(db%)\t%4!, {%1, %2, %3}"
[(set_attr "type" "store3") [(set_attr "type" "store3")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
...@@ -855,7 +871,8 @@ ...@@ -855,7 +871,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldm%(ia%)\t%3, {%1, %2}" "ldm%(ia%)\t%3, {%1, %2}"
[(set_attr "type" "load2") [(set_attr "type" "load2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_ldm2_ia" (define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -880,7 +897,8 @@ ...@@ -880,7 +897,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%(ia%)\t%3!, {%1, %2}" "ldm%(ia%)\t%3!, {%1, %2}"
[(set_attr "type" "load2") [(set_attr "type" "load2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_ldm2_ia_update" (define_insn "*thumb_ldm2_ia_update"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -904,7 +922,8 @@ ...@@ -904,7 +922,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%(ia%)\t%3, {%1, %2}" "stm%(ia%)\t%3, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm2_ia_update" (define_insn "*stm2_ia_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -917,7 +936,8 @@ ...@@ -917,7 +936,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(ia%)\t%3!, {%1, %2}" "stm%(ia%)\t%3!, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*thumb_stm2_ia_update" (define_insn "*thumb_stm2_ia_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -1044,7 +1064,8 @@ ...@@ -1044,7 +1064,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldm%(db%)\t%3, {%1, %2}" "ldm%(db%)\t%3, {%1, %2}"
[(set_attr "type" "load2") [(set_attr "type" "load2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*ldm2_db_update" (define_insn "*ldm2_db_update"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
...@@ -1059,7 +1080,8 @@ ...@@ -1059,7 +1080,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%(db%)\t%3!, {%1, %2}" "ldm%(db%)\t%3!, {%1, %2}"
[(set_attr "type" "load2") [(set_attr "type" "load2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm2_db" (define_insn "*stm2_db"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -1070,7 +1092,8 @@ ...@@ -1070,7 +1092,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%(db%)\t%3, {%1, %2}" "stm%(db%)\t%3, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "*stm2_db_update" (define_insn "*stm2_db_update"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
...@@ -1083,7 +1106,8 @@ ...@@ -1083,7 +1106,8 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%(db%)\t%3!, {%1, %2}" "stm%(db%)\t%3!, {%1, %2}"
[(set_attr "type" "store2") [(set_attr "type" "store2")
(set_attr "predicable" "yes")]) (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
......
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