Skip to content

R
riscv-gcc-1
Commit 0d9e23f4 by Richard Henderson Committed by Richard Henderson
Options

mn10300: fp insn cleanup 

Delete integer-mode abssf2, negsf2; these will be handled
by the middle-end now.  Delete unnecessary expanders.

From-SVN: r168673
parent c157b3f0
Showing with 27 additions and 190 deletions
gcc/ChangeLog
2011-01-11 Richard Henderson <rth@redhat.com>
* config/mn10300/mn10300.md (absdf2, negdf2): Remove.
(abssf2, negsf2): Define only for hardware fp.
(sqrtsf2): Reformat.
(addsf3, subsf3, mulsf3): Merge expander and insn.
* config/mn10300/mn10300.h (ARG_PIONTER_CFA_OFFSET): New.
(DEBUGGER_AUTO_OFFSET): Remove.
(DEBUGGER_ARG_OFFSET): Remove.
......
gcc/config/mn10300/mn10300.md
......@@ -2577,74 +2577,8 @@
;; ----------------------------------------------------------------------
;; FP INSTRUCTIONS
;; ----------------------------------------------------------------------
;;
;; The mn103 series does not have floating point instructions, but since
;; FP values are held in integer regs, we can clear the high bit easily
;; which gives us an efficient inline floating point absolute value.
;;
;; Similarly for negation of a FP value.
;;
(define_expand "absdf2"
[(set (match_operand:DF 0 "register_operand")
(abs:DF (match_operand:DF 1 "register_operand")))]
""
"
{
rtx target, result, insns;
start_sequence ();
target = operand_subword (operands[0], 1, 1, DFmode);
result = expand_binop (SImode, and_optab,
operand_subword_force (operands[1], 1, DFmode),
GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
gcc_assert (result);
if (result != target)
emit_move_insn (result, target);
emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
operand_subword_force (operands[1], 0, DFmode));
insns = get_insns ();
end_sequence ();
emit_insn (insns);
DONE;
}")
(define_expand "abssf2"
[(set (match_operand:SF 0 "register_operand")
(abs:SF (match_operand:SF 1 "register_operand")))]
""
"
{
rtx result;
rtx target;
if (TARGET_AM33_2)
{
emit_insn (gen_abssf2_am33_2 (operands[0], operands[1]));
DONE;
}
target = operand_subword_force (operands[0], 0, SFmode);
result = expand_binop (SImode, and_optab,
operand_subword_force (operands[1], 0, SFmode),
GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
gcc_assert (result);
if (result != target)
emit_move_insn (result, target);
/* Make a place for REG_EQUAL. */
emit_move_insn (operands[0], operands[0]);
DONE;
}")
(define_insn "abssf2_am33_2"
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
"TARGET_AM33_2"
......@@ -2655,67 +2589,7 @@
(const_int 17) (const_int 14)))]
)
(define_expand "negdf2"
[(set (match_operand:DF 0 "register_operand")
(neg:DF (match_operand:DF 1 "register_operand")))]
""
"
{
rtx target, result, insns;
start_sequence ();
target = operand_subword (operands[0], 1, 1, DFmode);
result = expand_binop (SImode, xor_optab,
operand_subword_force (operands[1], 1, DFmode),
GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
target, 0, OPTAB_WIDEN);
gcc_assert (result);
if (result != target)
emit_move_insn (result, target);
emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
operand_subword_force (operands[1], 0, DFmode));
insns = get_insns ();
end_sequence ();
emit_insn (insns);
DONE;
}")
(define_expand "negsf2"
[(set (match_operand:SF 0 "register_operand")
(neg:SF (match_operand:SF 1 "register_operand")))]
""
"
{
rtx result;
rtx target;
if (TARGET_AM33_2)
{
emit_insn (gen_negsf2_am33_2 (operands[0], operands[1]));
DONE;
}
target = operand_subword_force (operands[0], 0, SFmode);
result = expand_binop (SImode, xor_optab,
operand_subword_force (operands[1], 0, SFmode),
GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
target, 0, OPTAB_WIDEN);
gcc_assert (result);
if (result != target)
emit_move_insn (result, target);
/* Make a place for REG_EQUAL. */
emit_move_insn (operands[0], operands[0]);
DONE;
}")
(define_insn "negsf2_am33_2"
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
"TARGET_AM33_2"
......@@ -2727,27 +2601,22 @@
)
(define_expand "sqrtsf2"
[(parallel [(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC_FLOAT CC_REG))
])
]
[(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "register_operand" "")))]
"TARGET_AM33_2 && flag_unsafe_math_optimizations"
"
{
rtx scratch = gen_reg_rtx (SFmode);
emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
scratch));
DONE;
}")
{
rtx scratch = gen_reg_rtx (SFmode);
emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
scratch));
DONE;
})
(define_insn "rsqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
(sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
(clobber (reg:CC_FLOAT CC_REG))
]
(clobber (reg:CC_FLOAT CC_REG))]
"TARGET_AM33_2"
"@
frsqrt %0
......@@ -2756,22 +2625,11 @@
(const_int 4753) (const_int 2327)))]
)
(define_expand "addsf3"
[(parallel [(set (match_operand:SF 0 "register_operand")
(plus:SF (match_operand:SF 1 "register_operand")
(match_operand:SF 2 "nonmemory_operand")))
(clobber (reg:CC_FLOAT CC_REG))])
]
"TARGET_AM33_2"
""
)
(define_insn "*addsf3_internal"
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "register_operand" "%0,f")
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
(clobber (reg:CC_FLOAT CC_REG))
]
(clobber (reg:CC_FLOAT CC_REG))]
"TARGET_AM33_2"
"@
fadd %2, %0
......@@ -2781,26 +2639,14 @@
(const_int 17) (const_int 14))
(if_then_else (eq_attr "cpu" "am34")
(const_int 17) (const_int 25))
])
]
)
(define_expand "subsf3"
[(parallel [(set (match_operand:SF 0 "register_operand")
(minus:SF (match_operand:SF 1 "register_operand")
(match_operand:SF 2 "nonmemory_operand")))
(clobber (reg:CC_FLOAT CC_REG))])
]
"TARGET_AM33_2"
""
])]
)
(define_insn "*subsf3_internal"
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,f")
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
(clobber (reg:CC_FLOAT CC_REG))
]
(clobber (reg:CC_FLOAT CC_REG))]
"TARGET_AM33_2"
"@
fsub %2, %0
......@@ -2810,21 +2656,10 @@
(const_int 17) (const_int 14))
(if_then_else (eq_attr "cpu" "am34")
(const_int 17) (const_int 25))
])
]
])]
)
(define_expand "mulsf3"
[(parallel [(set (match_operand:SF 0 "register_operand")
(mult:SF (match_operand:SF 1 "register_operand")
(match_operand:SF 2 "nonmemory_operand")))
(clobber (reg:CC_FLOAT CC_REG))])
]
"TARGET_AM33_2"
""
)
(define_insn "*mulsf3_internal"
(define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "register_operand" "%0,f")
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
......@@ -2839,16 +2674,14 @@
(const_int 17) (const_int 14))
(if_then_else (eq_attr "cpu" "am34")
(const_int 17) (const_int 25))
])
]
])]
)
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,f")
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
(clobber (reg:CC_FLOAT CC_REG))
]
(clobber (reg:CC_FLOAT CC_REG))]
"TARGET_AM33_2"
"@
fdiv %2, %0
......@@ -2858,8 +2691,7 @@
(const_int 2531) (const_int 1216))
(if_then_else (eq_attr "cpu" "am34")
(const_int 2531) (const_int 1317))
])
]
])]
)
(define_insn "fmasf4"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment