Skip to content

R
riscv-gcc-1
Commit 0d0b79a6 by Ramana Radhakrishnan Committed by Ramana Radhakrishnan
Options

Neon intrinsics TLC - remove dead code. 

2014-05-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/arm_neon_builtins.def (vadd, vsub): Only define the v2sf
	and v4sf versions.
	(vand, vorr, veor, vorn, vbic): Remove.
	* config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec): Adjust
	iterator.
	(neon_vsub_unspec): Likewise.
	(neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove.

From-SVN: r210218
parent 7e422c4f
Showing with 25 additions and 81 deletions
gcc/ChangeLog
2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm_neon_builtins.def (vadd, vsub): Only define the v2sf
and v4sf versions.
(vand, vorr, veor, vorn, vbic): Remove.
* config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec): Adjust
iterator.
(neon_vsub_unspec): Likewise.
(neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove.
2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm_neon.h (vadd_s8): GNU C implementation
(vadd_s16): Likewise.
(vadd_s32): Likewise.
......
gcc/config/arm/arm_neon_builtins.def
......@@ -18,8 +18,7 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
VAR10 (BINOP, vadd,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR2 (BINOP, vadd, v2sf, v4sf),
VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
......@@ -54,7 +53,7 @@ VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
VAR10 (BINOP, vsub, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR2 (BINOP, vsub, v2sf, v4sf),
VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
......@@ -199,14 +198,4 @@ VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
VAR9 (STORESTRUCT, vst4,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
VAR7 (STORESTRUCTLANE, vst4_lane,
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
VAR10 (LOGICBINOP, vand,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR10 (LOGICBINOP, vorr,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR10 (BINOP, veor,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR10 (LOGICBINOP, vbic,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
VAR10 (LOGICBINOP, vorn,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
gcc/config/arm/neon.md
......@@ -1842,9 +1842,9 @@
; good for plain vadd, vaddq.
(define_expand "neon_vadd<mode>"
[(match_operand:VDQX 0 "s_register_operand" "=w")
(match_operand:VDQX 1 "s_register_operand" "w")
(match_operand:VDQX 2 "s_register_operand" "w")
[(match_operand:VCVTF 0 "s_register_operand" "=w")
(match_operand:VCVTF 1 "s_register_operand" "w")
(match_operand:VCVTF 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
......@@ -1869,9 +1869,9 @@
; Used for intrinsics when flag_unsafe_math_optimizations is false.
(define_insn "neon_vadd<mode>_unspec"
[(set (match_operand:VDQX 0 "s_register_operand" "=w")
(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
(match_operand:VDQX 2 "s_register_operand" "w")]
[(set (match_operand:VCVTF 0 "s_register_operand" "=w")
(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
(match_operand:VCVTF 2 "s_register_operand" "w")]
UNSPEC_VADD))]
"TARGET_NEON"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
......@@ -2132,9 +2132,9 @@
)
(define_expand "neon_vsub<mode>"
[(match_operand:VDQX 0 "s_register_operand" "=w")
(match_operand:VDQX 1 "s_register_operand" "w")
(match_operand:VDQX 2 "s_register_operand" "w")
[(match_operand:VCVTF 0 "s_register_operand" "=w")
(match_operand:VCVTF 1 "s_register_operand" "w")
(match_operand:VCVTF 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
......@@ -2149,9 +2149,9 @@
; Used for intrinsics when flag_unsafe_math_optimizations is false.
(define_insn "neon_vsub<mode>_unspec"
[(set (match_operand:VDQX 0 "s_register_operand" "=w")
(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
(match_operand:VDQX 2 "s_register_operand" "w")]
[(set (match_operand:VCVTF 0 "s_register_operand" "=w")
(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
(match_operand:VCVTF 2 "s_register_operand" "w")]
UNSPEC_VSUB))]
"TARGET_NEON"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
......@@ -5357,61 +5357,6 @@
[(set_attr "type" "neon_store4_4reg<q>")]
)
(define_expand "neon_vand<mode>"
[(match_operand:VDQX 0 "s_register_operand" "")
(match_operand:VDQX 1 "s_register_operand" "")
(match_operand:VDQX 2 "neon_inv_logic_op2" "")
(match_operand:SI 3 "immediate_operand" "")]
"TARGET_NEON"
{
emit_insn (gen_and<mode>3 (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "neon_vorr<mode>"
[(match_operand:VDQX 0 "s_register_operand" "")
(match_operand:VDQX 1 "s_register_operand" "")
(match_operand:VDQX 2 "neon_logic_op2" "")
(match_operand:SI 3 "immediate_operand" "")]
"TARGET_NEON"
{
emit_insn (gen_ior<mode>3 (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "neon_veor<mode>"
[(match_operand:VDQX 0 "s_register_operand" "")
(match_operand:VDQX 1 "s_register_operand" "")
(match_operand:VDQX 2 "s_register_operand" "")
(match_operand:SI 3 "immediate_operand" "")]
"TARGET_NEON"
{
emit_insn (gen_xor<mode>3 (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "neon_vbic<mode>"
[(match_operand:VDQX 0 "s_register_operand" "")
(match_operand:VDQX 1 "s_register_operand" "")
(match_operand:VDQX 2 "neon_logic_op2" "")
(match_operand:SI 3 "immediate_operand" "")]
"TARGET_NEON"
{
emit_insn (gen_bic<mode>3_neon (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "neon_vorn<mode>"
[(match_operand:VDQX 0 "s_register_operand" "")
(match_operand:VDQX 1 "s_register_operand" "")
(match_operand:VDQX 2 "neon_inv_logic_op2" "")
(match_operand:SI 3 "immediate_operand" "")]
"TARGET_NEON"
{
emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
DONE;
})
(define_insn "neon_vec_unpack<US>_lo_<mode>"
[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
(SE:<V_unpack> (vec_select:<V_HALF>
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment