re PR target/25199 (crashing code output from -mtune=pentium4 but not -mtune=pentiumpro)

	PR target/25199
	* config/i386/i386.md (movqi_1): Only force imovx for alternative
	5 if operand 1 is not aligned.  Undo previous constraint change.
	* config/i386/predicates.md (aligned_operand): Use MEM_ALIGN.
testsuite/
	* gcc.target/i386/movq-2.c: New test.
	* gcc.target/i386/movq.c: Remove target i?86, instead add
	dg-require-effective-target ilp32.

From-SVN: r107955

gcc/ChangeLog

+2005-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/25199
+	* config/i386/i386.md (movqi_1): Only force imovx for alternative
+	5 if operand 1 is not aligned.  Undo previous constraint change.
+	* config/i386/predicates.md (aligned_operand): Use MEM_ALIGN.
+
 2005-12-02  Richard Guenther  <rguenther@suse.de>
 
 	* tree.h (build): Remove prototype.

gcc/config/i386/i386.md

@@ -1469,7 +1469,7 @@
 ;; partial register stall can be caused there.  Then we use movzx.
 (define_insn "*movqi_1"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
-	(match_operand:QI 1 "general_operand"      " q,qn,qm,q,rn,m ,qn"))]
+	(match_operand:QI 1 "general_operand"      " q,qn,qm,q,rn,qm,qn"))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
 {
   switch (get_attr_type (insn))
@@ -1485,7 +1485,8 @@
     }
 }
   [(set (attr "type")
-     (cond [(eq_attr "alternative" "5")
+     (cond [(and (eq_attr "alternative" "5")
+		 (not (match_operand:QI 1 "aligned_operand" "")))
 	      (const_string "imovx")
 	    (ne (symbol_ref "optimize_size") (const_int 0))
 	      (const_string "imov")
@@ -1495,7 +1496,7 @@
 		      (eq (symbol_ref "TARGET_QIMODE_MATH")
 			  (const_int 0))))
 	      (const_string "imov")
-	    (eq_attr "alternative" "3")
+	    (eq_attr "alternative" "3,5")
 	      (const_string "imovx")
 	    (and (ne (symbol_ref "TARGET_MOVX")
 		     (const_int 0))

gcc/config/i386/predicates.md

@@ -687,7 +687,7 @@
   return parts.seg == SEG_DEFAULT;
 })
 
-;; Return nonzero if the rtx is known aligned.
+;; Return nonzero if the rtx is known to be at least 32 bits aligned.
 (define_predicate "aligned_operand"
   (match_operand 0 "general_operand")
 {
@@ -701,6 +701,10 @@
   /* Don't even try to do any aligned optimizations with volatiles.  */
   if (MEM_VOLATILE_P (op))
     return 0;
+
+  if (MEM_ALIGN (op) >= 32)
+    return 1;
+
   op = XEXP (op, 0);
 
   /* Pushes and pops are only valid on the stack pointer.  */

gcc/testsuite/ChangeLog

+2005-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/25199
+	* gcc.target/i386/movq-2.c: New test.
+	* gcc.target/i386/movq.c: Remove target i?86, instead add
+	dg-require-effective-target ilp32.
+
 2005-12-02  Volker Reichelt  <reichelt@igpm.rwth-aachen.de>
 
 	PR c++/24103

gcc/testsuite/gcc.target/i386/movq-2.c

+/* PR target/25199 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-require-effective-target ilp32 } */
+
+struct S
+{
+  void *p[30];
+  unsigned char c[4];
+};
+
+unsigned char d;
+
+void
+foo (struct S *x)
+{
+  register unsigned char e __asm ("esi");
+  e = x->c[3];
+  __asm __volatile ("" : : "r" (e));
+  e = x->c[0];
+  __asm __volatile ("" : : "r" (e));
+}
+
+/* { dg-final { scan-assembler-not "movl\[ \t\]*123" } } */
+/* { dg-final { scan-assembler "movzbl\[ \t\]*123" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]*120" } } */

gcc/testsuite/gcc.target/i386/movq.c

-/* { dg-do compile { target "i?86*-*-*" } }
+/* { dg-do compile }
 /* { dg-options "-Os -march=pentium4 -mtune=prescott" } */
+/* { dg-require-effective-target ilp32 } */
+
 register char foo asm("edi");
 char x;
 int bar() {