Commit 0ccfc3ab by Joern Rennecke Committed by Joern Rennecke

predicates.md (move_double_src_operand): Check that misaligned addresses are offsettable.

        * config/epiphany/predicates.md (move_double_src_operand):
        Check that misaligned addresses are offsettable.
        (move_dest_operand): Likewise.
        * config/epiphany/epiphany.c (REG_OK_FOR_BASE_P): Don't force a
        misaligned stack address to reg+index.

From-SVN: r193894
parent 3000ffec
2012-11-28 Joern Rennecke <joern.rennecke@embecosm.com>
* config/epiphany/predicates.md (move_double_src_operand):
Check that misaligned addresses are offsettable.
(move_dest_operand): Likewise.
* config/epiphany/epiphany.c (REG_OK_FOR_BASE_P): Don't force a
misaligned stack address to reg+index.
2012-11-28 Oleg Raikhman <oleg@adapteva.com> 2012-11-28 Oleg Raikhman <oleg@adapteva.com>
* config/epiphany/epiphany.h (ASM_OUTPUT_ALIGN_WITH_NOP): Define. * config/epiphany/epiphany.h (ASM_OUTPUT_ALIGN_WITH_NOP): Define.
...@@ -1963,6 +1963,14 @@ epiphany_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) ...@@ -1963,6 +1963,14 @@ epiphany_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
return true; return true;
if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x)) if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x))
return true; return true;
/* If this is a misaligned stack access, don't force it to reg+index. */
if (GET_MODE_SIZE (mode) == 8
&& GET_CODE (x) == PLUS && XEXP (x, 0) == stack_pointer_rtx
/* Decomposed to SImode; GET_MODE_SIZE (SImode) == 4 */
&& !(INTVAL (XEXP (x, 1)) & 3)
&& INTVAL (XEXP (x, 1)) >= -2047 * 4
&& INTVAL (XEXP (x, 1)) <= 2046 * 4)
return true;
if (TARGET_POST_INC if (TARGET_POST_INC
&& (GET_CODE (x) == POST_DEC || GET_CODE (x) == POST_INC) && (GET_CODE (x) == POST_DEC || GET_CODE (x) == POST_INC)
&& RTX_OK_FOR_BASE_P (XEXP ((x), 0))) && RTX_OK_FOR_BASE_P (XEXP ((x), 0)))
......
...@@ -164,6 +164,9 @@ ...@@ -164,6 +164,9 @@
(define_predicate "move_double_src_operand" (define_predicate "move_double_src_operand"
(match_code "reg,subreg,mem,const_int,const_double,const_vector") (match_code "reg,subreg,mem,const_int,const_double,const_vector")
{ {
if (GET_CODE (op) == MEM && misaligned_operand (op, mode)
&& !address_operand (plus_constant (XEXP (op, 0), 4), SImode))
return 0;
return general_operand (op, mode); return general_operand (op, mode);
}) })
...@@ -188,6 +191,9 @@ ...@@ -188,6 +191,9 @@
return register_operand (op, mode); return register_operand (op, mode);
} }
case MEM : case MEM :
if (GET_MODE_SIZE (mode) == 8 && misaligned_operand (op, mode)
&& !address_operand (plus_constant (XEXP (op, 0), 4), SImode))
return 0;
return address_operand (XEXP (op, 0), mode); return address_operand (XEXP (op, 0), mode);
default : default :
return 0; return 0;
......
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