S/390: Fix vector fp unordered compares

V2DF mode was still hard-coded here.

gcc/ChangeLog:

2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.c (s390_expand_vec_compare): Use the new mode
	independent expanders.
	* config/s390/vector.md ("vec_cmpuneq", "vec_cmpltgt")
	("vec_ordered", "vec_unordered"): New expanders.

From-SVN: r253197

gcc/ChangeLog

 2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
+	* config/s390/s390.c (s390_expand_vec_compare): Use the new mode
+	independent expanders.
+	* config/s390/vector.md ("vec_cmpuneq", "vec_cmpltgt")
+	("vec_ordered", "vec_unordered"): New expanders.
+
+2017-09-26  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
 	* config/s390/s390.c (s390_preferred_simd_mode): Return V4SFmode
 	for SFmode.
 

gcc/config/s390/s390.c

@@ -6396,16 +6396,16 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond,
 	  /* UNLT: a u< b -> !(a >= b) */
 	case UNLT: cond = GE; neg_p = true;                break;
 	case UNEQ:
-	  emit_insn (gen_vec_cmpuneqv2df (target, cmp_op1, cmp_op2));
+	  emit_insn (gen_vec_cmpuneq (target, cmp_op1, cmp_op2));
 	  return;
 	case LTGT:
-	  emit_insn (gen_vec_cmpltgtv2df (target, cmp_op1, cmp_op2));
+	  emit_insn (gen_vec_cmpltgt (target, cmp_op1, cmp_op2));
 	  return;
 	case ORDERED:
-	  emit_insn (gen_vec_orderedv2df (target, cmp_op1, cmp_op2));
+	  emit_insn (gen_vec_ordered (target, cmp_op1, cmp_op2));
 	  return;
 	case UNORDERED:
-	  emit_insn (gen_vec_unorderedv2df (target, cmp_op1, cmp_op2));
+	  emit_insn (gen_vec_unordered (target, cmp_op1, cmp_op2));
 	  return;
 	default: break;
 	}

gcc/config/s390/vector.md

@@ -1406,6 +1406,22 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
+(define_expand "vec_cmpuneq"
+  [(match_operand 0 "register_operand" "")
+   (match_operand 1 "register_operand" "")
+   (match_operand 2 "register_operand" "")]
+  "TARGET_VX"
+{
+  if (GET_MODE (operands[1]) == V4SFmode)
+    emit_insn (gen_vec_cmpuneqv4sf (operands[0], operands[1], operands[2]));
+  else if (GET_MODE (operands[1]) == V2DFmode)
+    emit_insn (gen_vec_cmpuneqv2df (operands[0], operands[1], operands[2]));
+  else
+    gcc_unreachable ();
+
+  DONE;
+})
+
 ; LTGT a <> b -> a > b | b > a
 (define_expand "vec_cmpltgt<mode>"
   [(set (match_operand:<tointvec>         0 "register_operand" "=v")
@@ -1418,6 +1434,22 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
+(define_expand "vec_cmpltgt"
+  [(match_operand 0 "register_operand" "")
+   (match_operand 1 "register_operand" "")
+   (match_operand 2 "register_operand" "")]
+  "TARGET_VX"
+{
+  if (GET_MODE (operands[1]) == V4SFmode)
+    emit_insn (gen_vec_cmpltgtv4sf (operands[0], operands[1], operands[2]));
+  else if (GET_MODE (operands[1]) == V2DFmode)
+    emit_insn (gen_vec_cmpltgtv2df (operands[0], operands[1], operands[2]));
+  else
+    gcc_unreachable ();
+
+  DONE;
+})
+
 ; ORDERED (a, b): a >= b | b > a
 (define_expand "vec_ordered<mode>"
   [(set (match_operand:<tointvec>          0 "register_operand" "=v")
@@ -1430,6 +1462,22 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
+(define_expand "vec_ordered"
+  [(match_operand 0 "register_operand" "")
+   (match_operand 1 "register_operand" "")
+   (match_operand 2 "register_operand" "")]
+  "TARGET_VX"
+{
+  if (GET_MODE (operands[1]) == V4SFmode)
+    emit_insn (gen_vec_orderedv4sf (operands[0], operands[1], operands[2]));
+  else if (GET_MODE (operands[1]) == V2DFmode)
+    emit_insn (gen_vec_orderedv2df (operands[0], operands[1], operands[2]));
+  else
+    gcc_unreachable ();
+
+  DONE;
+})
+
 ; UNORDERED (a, b): !ORDERED (a, b)
 (define_expand "vec_unordered<mode>"
   [(set (match_operand:<tointvec>          0 "register_operand" "=v")
@@ -1443,6 +1491,22 @@
   operands[3] = gen_reg_rtx (<tointvec>mode);
 })
 
+(define_expand "vec_unordered"
+  [(match_operand 0 "register_operand" "")
+   (match_operand 1 "register_operand" "")
+   (match_operand 2 "register_operand" "")]
+  "TARGET_VX"
+{
+  if (GET_MODE (operands[1]) == V4SFmode)
+    emit_insn (gen_vec_unorderedv4sf (operands[0], operands[1], operands[2]));
+  else if (GET_MODE (operands[1]) == V2DFmode)
+    emit_insn (gen_vec_unorderedv2df (operands[0], operands[1], operands[2]));
+  else
+    gcc_unreachable ();
+
+  DONE;
+})
+
 (define_insn "*vec_load_pair<mode>"
   [(set (match_operand:V_HW_64                       0 "register_operand" "=v,v")
 	(vec_concat:V_HW_64 (match_operand:<non_vec> 1 "register_operand"  "d,v")