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Commit 0c8ac746 by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Delete "wJ" and "wK" constraints 

This replaces "wJ" by "wI", and "wK by "wH", both with isa "p9v".


	* config/rs6000/constraints.md (define_register_constraint "wJ"):
	Delete.
	(define_register_constraint "wK"): Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wJ and RS6000_CONSTRAINT_wK.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wJ" constraint by "wI" with "p9v".
	Replace "wK" constraint by "wH" with "p9v".
	* config/rs6000/vsx.md: Ditto.
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271387
parent d17fbef8
Showing with 39 additions and 43 deletions
gcc/ChangeLog
2019-05-19 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wJ"):
Delete.
(define_register_constraint "wK"): Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wJ and RS6000_CONSTRAINT_wK.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.md: Replace "wJ" constraint by "wI" with "p9v".
Replace "wK" constraint by "wH" with "p9v".
* config/rs6000/vsx.md: Ditto.
* doc/md.texi (Machine Constraints): Adjust.
2019-05-19 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wb"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
......
gcc/config/rs6000/constraints.md
......@@ -157,12 +157,6 @@
(define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]"
"FPR register to hold 32-bit integers or NO_REGS.")
(define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]"
"FPR register to hold 8/16-bit integers or NO_REGS.")
(define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]"
"Altivec register to hold 8/16-bit integers or NO_REGS.")
(define_constraint "wL"
"Int constant that is the element number mfvsrld accesses in a vector."
(and (match_code "const_int")
......
gcc/config/rs6000/rs6000.c
......@@ -2532,8 +2532,6 @@ rs6000_debug_reg_global (void)
"wA reg_class = %s\n"
"wH reg_class = %s\n"
"wI reg_class = %s\n"
"wJ reg_class = %s\n"
"wK reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
......@@ -2562,9 +2560,7 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]]);
nl = "\n";
for (m = 0; m < NUM_MACHINE_MODES; ++m)
......@@ -3192,9 +3188,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wy - Register class to do ISA 2.07 SF operations.
wz - Float register if we can do 32-bit unsigned int loads.
wH - Altivec register if SImode is allowed in VSX registers.
wI - Float register if SImode is allowed in VSX registers.
wJ - Float register if QImode/HImode are allowed in VSX registers.
wK - Altivec register if QImode/HImode are allowed in VSX registers. */
wI - Float register if SImode is allowed in VSX registers. */
if (TARGET_HARD_FLOAT)
{
......@@ -3271,11 +3265,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
{
rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
if (TARGET_P9_VECTOR)
{
rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
}
}
/* Set up the reload helper and direct move functions. */
gcc/config/rs6000/rs6000.h
......@@ -1273,8 +1273,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */
RS6000_CONSTRAINT_MAX
};
......
gcc/config/rs6000/vsx.md
......@@ -3525,7 +3525,7 @@
(define_insn "vsx_extract_<mode>_p9"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(vec_select:<VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,<VSX_EX>")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
(clobber (match_scratch:SI 3 "=r,X"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
......@@ -3550,7 +3550,8 @@
return "vextractu<wd> %0,%1,%2";
}
}
[(set_attr "type" "vecsimple")])
[(set_attr "type" "vecsimple")
(set_attr "isa" "p9v,*")])
(define_split
[(set (match_operand:<VS_scalar> 0 "int_reg_operand")
......@@ -3580,7 +3581,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,<VSX_EX>")
(zero_extend:DI
(vec_select:<VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,<VSX_EX>")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
(clobber (match_scratch:SI 3 "=r,X"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
......@@ -3593,7 +3594,8 @@
(clobber (match_dup 3))])]
{
operands[4] = gen_rtx_REG (<VS_scalar>mode, REGNO (operands[0]));
})
}
[(set_attr "isa" "p9v,*")])
;; Optimize stores to use the ISA 3.0 scalar store instructions
(define_insn_and_split "*vsx_extract_<mode>_store_p9"
......@@ -3617,9 +3619,9 @@
(define_insn_and_split "*vsx_extract_si"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,wHwI,Z")
(vec_select:SI
(match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv")
(match_operand:V4SI 1 "gpc_reg_operand" "v,v,v")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))
(clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))]
(clobber (match_scratch:V4SI 3 "=v,v,v"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
......@@ -3733,7 +3735,7 @@
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
(unspec:<VS_scalar>
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m")
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT))
(clobber (match_scratch:DI 3 "=r,r,&b"))
......@@ -3746,13 +3748,14 @@
rs6000_split_vec_extract_var (operands[0], operands[1], operands[2],
operands[3], operands[4]);
DONE;
})
}
[(set_attr "isa" "p9v,*,*")])
(define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
(zero_extend:<VS_scalar>
(unspec:<VSX_EXTRACT_I:VS_scalar>
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m")
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT)))
(clobber (match_scratch:DI 3 "=r,r,&b"))
......@@ -3767,7 +3770,8 @@
operands[1], operands[2],
operands[3], operands[4]);
DONE;
})
}
[(set_attr "isa" "p9v,*,*")])
;; VSX_EXTRACT optimizations
;; Optimize double d = (double) vec_extract (vi, <n>)
......@@ -3951,7 +3955,7 @@
(match_operand:SF 2 "gpc_reg_operand" "ww")
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
(clobber (match_scratch:SI 4 "=&wIwH"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
......@@ -3976,7 +3980,8 @@
operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
}
[(set_attr "type" "vecperm")
(set_attr "length" "12")])
(set_attr "length" "12")
(set_attr "isa" "p9v")])
;; Special case setting 0.0f to a V4SF element
(define_insn_and_split "*vsx_set_v4sf_p9_zero"
......@@ -3986,7 +3991,7 @@
(match_operand:SF 2 "zero_fp_constant" "j")
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
(clobber (match_scratch:SI 4 "=&wIwH"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
......@@ -4001,7 +4006,8 @@
operands[5] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
}
[(set_attr "type" "vecperm")
(set_attr "length" "8")])
(set_attr "length" "8")
(set_attr "isa" "p9v")])
;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is the element
;; that is in the default scalar position (1 for big endian, 2 for little
......@@ -4043,7 +4049,7 @@
[(match_operand:QI 3 "const_0_to_3_operand" "n")]))
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
(clobber (match_scratch:SI 5 "=&wIwH"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
&& TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (BYTES_BIG_ENDIAN ? 1 : 2))"
......@@ -4066,7 +4072,8 @@
operands[7] = gen_lowpart (V4SImode, operands[0]);
operands[8] = gen_lowpart (V4SImode, operands[1]);
}
[(set_attr "type" "vecperm")])
[(set_attr "type" "vecperm")
(set_attr "isa" "p9v")])
;; Expanders for builtins
(define_expand "vsx_mergel_<mode>"
......
gcc/doc/md.texi
......@@ -3337,12 +3337,6 @@ Altivec register if @option{-mvsx-small-integer}.
@item wI
Floating point register if @option{-mvsx-small-integer}.
@item wJ
FP register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
@item wK
Altivec register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
@item wL
Int constant that is the element number that the MFVSRLD instruction.
targets.
......
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