Skip to content

R
riscv-gcc-1
Commit 0bf86d46 by Kelvin Nilsen
Options

rs6000-builtin.def: Remove various BU_ALTIVEC_X macro expansions for definition of... 

gcc/ChangeLog:

2018-03-22  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/rs6000-builtin.def: Remove various BU_ALTIVEC_X
	macro expansions for definition of ST_INTERNAL_<mode> and
	LD_INTERNAL_<mode> builtins.
	* config/rs6000/rs6000-protos.h (rs6000_address_for_altivec):
	Remove prototype.
	* config/rs6000/rs6000.c (altivec_expand_ld_builtin): Delete this
	function.
	(altivec_expand_st_builtin): Likewise.
	(altivec_expand_builtin): Remove calls to deleted functions.
	(rs6000_address_for_altivec): Delete this function.
	* config/rs6000/vector.md: Remove expands for
	vector_altivec_load_<mode> and vector_altivec_store_<mode>.

From-SVN: r258783
parent bb4ac03b
Showing with 15 additions and 205 deletions
gcc/ChangeLog
2018-03-22 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def: Remove various BU_ALTIVEC_X
macro expansions for definition of ST_INTERNAL_<mode> and
LD_INTERNAL_<mode> builtins.
* config/rs6000/rs6000-protos.h (rs6000_address_for_altivec):
Remove prototype.
* config/rs6000/rs6000.c (altivec_expand_ld_builtin): Delete this
function.
(altivec_expand_st_builtin): Likewise.
(altivec_expand_builtin): Remove calls to deleted functions.
(rs6000_address_for_altivec): Delete this function.
* config/rs6000/vector.md: Remove expands for
vector_altivec_load_<mode> and vector_altivec_store_<mode>.
2018-03-22 Sudakshina Das <sudi.das@arm.com>
PR target/84826
......
gcc/config/rs6000/rs6000-builtin.def
......@@ -1210,20 +1210,6 @@ BU_ALTIVEC_P (VCMPGTSB_P, "vcmpgtsb_p", CONST, vector_gt_v16qi_p)
BU_ALTIVEC_P (VCMPGTUB_P, "vcmpgtub_p", CONST, vector_gtu_v16qi_p)
/* AltiVec builtins that are handled as special cases. */
BU_ALTIVEC_X (ST_INTERNAL_4si, "st_internal_4si", MEM)
BU_ALTIVEC_X (LD_INTERNAL_4si, "ld_internal_4si", MEM)
BU_ALTIVEC_X (ST_INTERNAL_8hi, "st_internal_8hi", MEM)
BU_ALTIVEC_X (LD_INTERNAL_8hi, "ld_internal_8hi", MEM)
BU_ALTIVEC_X (ST_INTERNAL_16qi, "st_internal_16qi", MEM)
BU_ALTIVEC_X (LD_INTERNAL_16qi, "ld_internal_16qi", MEM)
BU_ALTIVEC_X (ST_INTERNAL_4sf, "st_internal_16qi", MEM)
BU_ALTIVEC_X (LD_INTERNAL_4sf, "ld_internal_4sf", MEM)
BU_ALTIVEC_X (ST_INTERNAL_2df, "st_internal_4sf", MEM)
BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM)
BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM)
BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM)
BU_ALTIVEC_X (ST_INTERNAL_1ti, "st_internal_1ti", MEM)
BU_ALTIVEC_X (LD_INTERNAL_1ti, "ld_internal_1ti", MEM)
BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC)
BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC)
BU_ALTIVEC_X (DSSALL, "dssall", MISC)
......
gcc/config/rs6000/rs6000-protos.h
......@@ -162,7 +162,6 @@ extern void rs6000_emit_parity (rtx, rtx);
extern rtx rs6000_machopic_legitimize_pic_address (rtx, machine_mode,
rtx);
extern rtx rs6000_address_for_fpconvert (rtx);
extern rtx rs6000_address_for_altivec (rtx);
extern rtx rs6000_allocate_stack_temp (machine_mode, bool, bool);
extern int rs6000_loop_align (rtx);
extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool);
......
gcc/config/rs6000/rs6000.c
......@@ -15184,126 +15184,6 @@ rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
return target;
}
/* Expand the lvx builtins. */
static rtx
altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
{
tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
tree arg0;
machine_mode tmode, mode0;
rtx pat, op0;
enum insn_code icode;
switch (fcode)
{
case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
icode = CODE_FOR_vector_altivec_load_v16qi;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
icode = CODE_FOR_vector_altivec_load_v8hi;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
icode = CODE_FOR_vector_altivec_load_v4si;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
icode = CODE_FOR_vector_altivec_load_v4sf;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
icode = CODE_FOR_vector_altivec_load_v2df;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
icode = CODE_FOR_vector_altivec_load_v2di;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
icode = CODE_FOR_vector_altivec_load_v1ti;
break;
default:
*expandedp = false;
return NULL_RTX;
}
*expandedp = true;
arg0 = CALL_EXPR_ARG (exp, 0);
op0 = expand_normal (arg0);
tmode = insn_data[icode].operand[0].mode;
mode0 = insn_data[icode].operand[1].mode;
if (target == 0
|| GET_MODE (target) != tmode
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
pat = GEN_FCN (icode) (target, op0);
if (! pat)
return 0;
emit_insn (pat);
return target;
}
/* Expand the stvx builtins. */
static rtx
altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
bool *expandedp)
{
tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
tree arg0, arg1;
machine_mode mode0, mode1;
rtx pat, op0, op1;
enum insn_code icode;
switch (fcode)
{
case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
icode = CODE_FOR_vector_altivec_store_v16qi;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
icode = CODE_FOR_vector_altivec_store_v8hi;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
icode = CODE_FOR_vector_altivec_store_v4si;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
icode = CODE_FOR_vector_altivec_store_v4sf;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
icode = CODE_FOR_vector_altivec_store_v2df;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
icode = CODE_FOR_vector_altivec_store_v2di;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
icode = CODE_FOR_vector_altivec_store_v1ti;
break;
default:
*expandedp = false;
return NULL_RTX;
}
arg0 = CALL_EXPR_ARG (exp, 0);
arg1 = CALL_EXPR_ARG (exp, 1);
op0 = expand_normal (arg0);
op1 = expand_normal (arg1);
mode0 = insn_data[icode].operand[0].mode;
mode1 = insn_data[icode].operand[1].mode;
if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
op1 = copy_to_mode_reg (mode1, op1);
pat = GEN_FCN (icode) (op0, op1);
if (pat)
emit_insn (pat);
*expandedp = true;
return NULL_RTX;
}
/* Expand the dst builtins. */
static rtx
......@@ -15508,14 +15388,6 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
return expand_call (exp, target, false);
}
target = altivec_expand_ld_builtin (exp, target, expandedp);
if (*expandedp)
return target;
target = altivec_expand_st_builtin (exp, target, expandedp);
if (*expandedp)
return target;
target = altivec_expand_dst_builtin (exp, target, expandedp);
if (*expandedp)
return target;
......@@ -38011,29 +37883,6 @@ rs6000_address_for_fpconvert (rtx x)
return x;
}
/* Given a memory reference, if it is not in the form for altivec memory
reference instructions (i.e. reg or reg+reg addressing with AND of -16),
convert to the altivec format. */
rtx
rs6000_address_for_altivec (rtx x)
{
gcc_assert (MEM_P (x));
if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
{
rtx addr = XEXP (x, 0);
if (!legitimate_indexed_address_p (addr, reload_completed)
&& !legitimate_indirect_address_p (addr, reload_completed))
addr = copy_to_mode_reg (Pmode, addr);
addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
x = change_address (x, GET_MODE (x), addr);
}
return x;
}
/* Implement TARGET_LEGITIMATE_CONSTANT_P.
On the RS/6000, all integer constants are acceptable, most won't be valid
gcc/config/rs6000/vector.md
......@@ -180,45 +180,6 @@
DONE;
})
;; Vector floating point load/store instructions that uses the Altivec
;; instructions even if we are compiling for VSX, since the Altivec
;; instructions silently ignore the bottom 3 bits of the address, and VSX does
;; not.
(define_expand "vector_altivec_load_<mode>"
[(set (match_operand:VEC_M 0 "vfloat_operand")
(match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
if (VECTOR_MEM_VSX_P (<MODE>mode))
{
operands[1] = rs6000_address_for_altivec (operands[1]);
rtx and_op = XEXP (operands[1], 0);
gcc_assert (GET_CODE (and_op) == AND);
emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
DONE;
}
})
(define_expand "vector_altivec_store_<mode>"
[(set (match_operand:VEC_M 0 "memory_operand")
(match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
if (VECTOR_MEM_VSX_P (<MODE>mode))
{
operands[0] = rs6000_address_for_altivec (operands[0]);
rtx and_op = XEXP (operands[0], 0);
gcc_assert (GET_CODE (and_op) == AND);
emit_insn (gen_altivec_stvx_<mode> (operands[1], operands[0]));
DONE;
}
})
;; Generic floating point vector arithmetic support
(define_expand "add<mode>3"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment