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riscv-gcc-1
Commit 0be8bd1a by Richard Earnshaw Committed by Richard Earnshaw
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arm.h (TARGET_CPU_CPP_BUILTINS): Remove Maverick support. 

	* arm.h (TARGET_CPU_CPP_BUILTINS): Remove Maverick support.
	(TARGET_FPA): Delete definition.
	(TARGET_MAVERICK): Likewise.
	(TARGET_FPA_EMU2): Likewise.
	(arm_fp_model): Remove FPA and Maverick models.
	(arm_arch_cirrus): Delete declaration.
	(FLOAT_WORDS_BIG_ENDIAN): Delete definition.
	(FIXED_REGISTERS): Remove FPA and Maverick support.  Reorganize.
	(CALL_USED_REGISTERS): Likewise.
	(FIRST_FPA_REGNUM, LAST_FPA_REGNUM): Delete definition.
	(FIRST_VFP_REGNUM): Renumbered.
	(D7_VFP_REGNUM): Chain definition.
	(LAST_LO_VFP_REGNUM): Likewise.
	(FIRST_HI_VFP_REGNUM): Likewise.
	(LAST_HI_VFP_REGNUM): Likewise.
	(FIRST_IWMMXT_GR_REGNUM): Likewise.
	(LAST_IWMMXT_GR_REGNUM): Likewise.
	(FIRST_IWMMXT_REGNUM): Likewise.
	(LAST_IWMMXT_REGNUM): Likewise.
	(FRAME_POINTER_REGNUM): Renumbered.
	(ARG_POINTER_REGNUM): Renumbered.
	(FIRST_PSEUDO_REGISTER): Remove FPA and Maverick registers.
	(FIRST_CIRRUS_FP_REGNUM, LAST_CIRRUS_FP_REGNUM): Delete definitions.
	(HARD_REGNO_REGNUM): Remove FPA support.
	(REG_ALLOC_ORDER): Remove FPA and Maverick registers.  Reorganize.
	(reg_class): Likewise.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	(CANNOT_CHANGE_MODE_CLASS): Never true.  Update comment.
	(SECONDARY_INPUT_RELOAD_CLASS): Remove Maverick support.
	(CLASS_MAX_NREGS): Remove FPA and Maverick support.
	* aout.h (REGISTER_NAMES): Remove FPA and Maverick registers.
	Reorganize.  Use AAPCS preferred names.
	(ADDITIONAL_REGISTER_NAMES): Remove aliases for Maverick.  Update
	comments.
	(OVERLAPPING_REGISTER_NAMES): Update register numbering.
	* arm.c (FL_CIRRUS): Delete definition.
	(arm_arch_cirrus): Delete variable.
	(arm_float_words_big_endian): Delete function.
	(cirrus_memory_offset): Delete function.
	(output_mov_long_double_fpa_from_arm): Delete function.
	(output_mov_long_double_arm_from_fpa): Delete function.
	(output_mov_double_fpa_from_arm): Delete function.
	(output_mov_double_arm_from_fpa): Delete function.
	(emit_sfm): Delete function.
	(maybe_get_arm_condition_code): Update comment.
	(arm_file_start): Always use softvfp for softfloat systems.
	(thumb_core_reg_alloc_order): Adjust for updated register allocation.
	(arm_option_override): Remove FPA and Maverick support.  Always
	default to vfp as the fallback FPU format.
	(use_return_insn): Remove FPA support.
	(arm_get_frame_offsets): Likewise.
	(arm_save_coproc_regs): Likewise.
	(arm_canonicalize_comparison): Remove Maverick support.
	(arm_select_cc_mode): Likewise.
	(arm_gen_compare_reg): Likewise.
	(arm_print_operand): Likewise.
	(arm_libcall_value_1): Remove FPA and Maverick support.
	(arm_function_value_regno_p): Likewise.
	(arm_apply_result_size): Likewise.
	(arm_legitimate_index_p): Likewise.
	(thumb2_legitimate_index_p): Likewise.
	(legitimize_reload_address): Likewise.
	(arm_register_move_cost): Likewise.
	(arm_hard_regno_mode_ok): Likewise.
	(arm_regno_class): Likewise.
	(arm_dbx_register_number): Likewise.
	(arm_emit_unwind_sequence): Likewise.
	(arm_conditional_register_usage): Likewise.
	* arm-protos.h (neg_const_double_rtx_ok_for_fpa): Remove declaration.
	(cirrus_memory_offset): Likewise.
	(output_move_long_double_fpa_from_arm): Likewise.
	(output_move_long_double_arm_from_fpa): Likewise.
	(output_move_double_fpa_from_arm): Likewise.
	(output_move_double_arm_from_fpa): Likewise.
	(arm_float_words_big_endian): Likewise.
	* arm.md (CC_REGNUM): Renumbered.
	(VFPCC_REGNUM): Moved here.  Renumbered.
	(FPA_F0_REGNUM, FPA_F7_REGNUM): Delete.
	(attr fpu): Remove FPA and Maverick support.
	* vfp.md (VFPCC_REGNUM): Delete.  Moved to arm.md.
	* arm-cores.def (ep9312): Remove Maverick support.
	* arm-arches.def (ep9312): Delete architecture.
	* arm-tables.opt: Regenerated.

	* arm/linux-elf.h (FPUTYPE_DEFAULT): Set to vfp.

From-SVN: r189350
parent 8166ff4d
Showing with 158 additions and 158 deletions
gcc/ChangeLog
2012-07-07 Richard Earnshaw <rearnsha@arm.com>
* arm.h (TARGET_CPU_CPP_BUILTINS): Remove Maverick support.
(TARGET_FPA): Delete definition.
(TARGET_MAVERICK): Likewise.
(TARGET_FPA_EMU2): Likewise.
(arm_fp_model): Remove FPA and Maverick models.
(arm_arch_cirrus): Delete declaration.
(FLOAT_WORDS_BIG_ENDIAN): Delete definition.
(FIXED_REGISTERS): Remove FPA and Maverick support. Reorganize.
(CALL_USED_REGISTERS): Likewise.
(FIRST_FPA_REGNUM, LAST_FPA_REGNUM): Delete definition.
(FIRST_VFP_REGNUM): Renumbered.
(D7_VFP_REGNUM): Chain definition.
(LAST_LO_VFP_REGNUM): Likewise.
(FIRST_HI_VFP_REGNUM): Likewise.
(LAST_HI_VFP_REGNUM): Likewise.
(FIRST_IWMMXT_GR_REGNUM): Likewise.
(LAST_IWMMXT_GR_REGNUM): Likewise.
(FIRST_IWMMXT_REGNUM): Likewise.
(LAST_IWMMXT_REGNUM): Likewise.
(FRAME_POINTER_REGNUM): Renumbered.
(ARG_POINTER_REGNUM): Renumbered.
(FIRST_PSEUDO_REGISTER): Remove FPA and Maverick registers.
(FIRST_CIRRUS_FP_REGNUM, LAST_CIRRUS_FP_REGNUM): Delete definitions.
(HARD_REGNO_REGNUM): Remove FPA support.
(REG_ALLOC_ORDER): Remove FPA and Maverick registers. Reorganize.
(reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(CANNOT_CHANGE_MODE_CLASS): Never true. Update comment.
(SECONDARY_INPUT_RELOAD_CLASS): Remove Maverick support.
(CLASS_MAX_NREGS): Remove FPA and Maverick support.
* aout.h (REGISTER_NAMES): Remove FPA and Maverick registers.
Reorganize. Use AAPCS preferred names.
(ADDITIONAL_REGISTER_NAMES): Remove aliases for Maverick. Update
comments.
(OVERLAPPING_REGISTER_NAMES): Update register numbering.
* arm.c (FL_CIRRUS): Delete definition.
(arm_arch_cirrus): Delete variable.
(arm_float_words_big_endian): Delete function.
(cirrus_memory_offset): Delete function.
(output_mov_long_double_fpa_from_arm): Delete function.
(output_mov_long_double_arm_from_fpa): Delete function.
(output_mov_double_fpa_from_arm): Delete function.
(output_mov_double_arm_from_fpa): Delete function.
(emit_sfm): Delete function.
(maybe_get_arm_condition_code): Update comment.
(arm_file_start): Always use softvfp for softfloat systems.
(thumb_core_reg_alloc_order): Adjust for updated register allocation.
(arm_option_override): Remove FPA and Maverick support. Always
default to vfp as the fallback FPU format.
(use_return_insn): Remove FPA support.
(arm_get_frame_offsets): Likewise.
(arm_save_coproc_regs): Likewise.
(arm_canonicalize_comparison): Remove Maverick support.
(arm_select_cc_mode): Likewise.
(arm_gen_compare_reg): Likewise.
(arm_print_operand): Likewise.
(arm_libcall_value_1): Remove FPA and Maverick support.
(arm_function_value_regno_p): Likewise.
(arm_apply_result_size): Likewise.
(arm_legitimate_index_p): Likewise.
(thumb2_legitimate_index_p): Likewise.
(legitimize_reload_address): Likewise.
(arm_register_move_cost): Likewise.
(arm_hard_regno_mode_ok): Likewise.
(arm_regno_class): Likewise.
(arm_dbx_register_number): Likewise.
(arm_emit_unwind_sequence): Likewise.
(arm_conditional_register_usage): Likewise.
* arm-protos.h (neg_const_double_rtx_ok_for_fpa): Remove declaration.
(cirrus_memory_offset): Likewise.
(output_move_long_double_fpa_from_arm): Likewise.
(output_move_long_double_arm_from_fpa): Likewise.
(output_move_double_fpa_from_arm): Likewise.
(output_move_double_arm_from_fpa): Likewise.
(arm_float_words_big_endian): Likewise.
* arm.md (CC_REGNUM): Renumbered.
(VFPCC_REGNUM): Moved here. Renumbered.
(FPA_F0_REGNUM, FPA_F7_REGNUM): Delete.
(attr fpu): Remove FPA and Maverick support.
* vfp.md (VFPCC_REGNUM): Delete. Moved to arm.md.
* arm-cores.def (ep9312): Remove Maverick support.
* arm-arches.def (ep9312): Delete architecture.
* arm-tables.opt: Regenerated.
* arm/linux-elf.h (FPUTYPE_DEFAULT): Set to vfp.
2012-07-07 Steven Bosscher <steven@gcc.gnu.org>
PR tree-optimization/53881
......
gcc/config/arm/aout.h
......@@ -51,30 +51,24 @@
(each of which is overlaid on two S registers), although there are no
actual single-precision registers which correspond to D16-D31. */
#ifndef REGISTER_NAMES
#define REGISTER_NAMES \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
"cc", "sfp", "afp", \
"mv0", "mv1", "mv2", "mv3", \
"mv4", "mv5", "mv6", "mv7", \
"mv8", "mv9", "mv10", "mv11", \
"mv12", "mv13", "mv14", "mv15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
"wr0", "wr1", "wr2", "wr3", \
"wr4", "wr5", "wr6", "wr7", \
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
"d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
"d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
"d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
"d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
"vfpcc" \
#define REGISTER_NAMES \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc", \
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
"d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
"d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
"d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
"d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
"wr0", "wr1", "wr2", "wr3", \
"wr4", "wr5", "wr6", "wr7", \
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
"cc", "vfpcc", "sfp", "afp" \
}
#endif
......@@ -91,117 +85,53 @@
{"v4", 7}, \
{"v5", 8}, \
{"v6", 9}, \
{"rfp", 9}, /* Gcc used to call it this */ \
{"sb", 9}, \
{"rfp", 9}, /* Historical. */ \
{"sb", 9}, /* Historical. */ \
{"v7", 10}, \
{"r10", 10}, /* sl */ \
{"sl", 10}, /* Historical. */ \
{"r11", 11}, /* fp */ \
{"r12", 12}, /* ip */ \
{"r13", 13}, /* sp */ \
{"r14", 14}, /* lr */ \
{"r15", 15}, /* pc */ \
{"mvf0", 27}, \
{"mvf1", 28}, \
{"mvf2", 29}, \
{"mvf3", 30}, \
{"mvf4", 31}, \
{"mvf5", 32}, \
{"mvf6", 33}, \
{"mvf7", 34}, \
{"mvf8", 35}, \
{"mvf9", 36}, \
{"mvf10", 37}, \
{"mvf11", 38}, \
{"mvf12", 39}, \
{"mvf13", 40}, \
{"mvf14", 41}, \
{"mvf15", 42}, \
{"mvd0", 27}, \
{"mvd1", 28}, \
{"mvd2", 29}, \
{"mvd3", 30}, \
{"mvd4", 31}, \
{"mvd5", 32}, \
{"mvd6", 33}, \
{"mvd7", 34}, \
{"mvd8", 35}, \
{"mvd9", 36}, \
{"mvd10", 37}, \
{"mvd11", 38}, \
{"mvd12", 39}, \
{"mvd13", 40}, \
{"mvd14", 41}, \
{"mvd15", 42}, \
{"mvfx0", 27}, \
{"mvfx1", 28}, \
{"mvfx2", 29}, \
{"mvfx3", 30}, \
{"mvfx4", 31}, \
{"mvfx5", 32}, \
{"mvfx6", 33}, \
{"mvfx7", 34}, \
{"mvfx8", 35}, \
{"mvfx9", 36}, \
{"mvfx10", 37}, \
{"mvfx11", 38}, \
{"mvfx12", 39}, \
{"mvfx13", 40}, \
{"mvfx14", 41}, \
{"mvfx15", 42}, \
{"mvdx0", 27}, \
{"mvdx1", 28}, \
{"mvdx2", 29}, \
{"mvdx3", 30}, \
{"mvdx4", 31}, \
{"mvdx5", 32}, \
{"mvdx6", 33}, \
{"mvdx7", 34}, \
{"mvdx8", 35}, \
{"mvdx9", 36}, \
{"mvdx10", 37}, \
{"mvdx11", 38}, \
{"mvdx12", 39}, \
{"mvdx13", 40}, \
{"mvdx14", 41}, \
{"mvdx15", 42} \
{"r15", 15} /* pc */ \
}
#endif
#ifndef OVERLAPPING_REGISTER_NAMES
#define OVERLAPPING_REGISTER_NAMES \
{ \
{"d0", 63, 2}, \
{"d1", 65, 2}, \
{"d2", 67, 2}, \
{"d3", 69, 2}, \
{"d4", 71, 2}, \
{"d5", 73, 2}, \
{"d6", 75, 2}, \
{"d7", 77, 2}, \
{"d8", 79, 2}, \
{"d9", 81, 2}, \
{"d10", 83, 2}, \
{"d11", 85, 2}, \
{"d12", 87, 2}, \
{"d13", 89, 2}, \
{"d14", 91, 2}, \
{"d15", 93, 2}, \
{"q0", 63, 4}, \
{"q1", 67, 4}, \
{"q2", 71, 4}, \
{"q3", 75, 4}, \
{"q4", 79, 4}, \
{"q5", 83, 4}, \
{"q6", 87, 4}, \
{"q7", 91, 4}, \
{"q8", 95, 4}, \
{"q9", 99, 4}, \
{"q10", 103, 4}, \
{"q11", 107, 4}, \
{"q12", 111, 4}, \
{"q13", 115, 4}, \
{"q14", 119, 4}, \
{"q15", 123, 4} \
{"d0", FIRST_VFP_REGNUM + 0, 2}, \
{"d1", FIRST_VFP_REGNUM + 2, 2}, \
{"d2", FIRST_VFP_REGNUM + 4, 2}, \
{"d3", FIRST_VFP_REGNUM + 6, 2}, \
{"d4", FIRST_VFP_REGNUM + 8, 2}, \
{"d5", FIRST_VFP_REGNUM + 10, 2}, \
{"d6", FIRST_VFP_REGNUM + 12, 2}, \
{"d7", FIRST_VFP_REGNUM + 14, 2}, \
{"d8", FIRST_VFP_REGNUM + 16, 2}, \
{"d9", FIRST_VFP_REGNUM + 18, 2}, \
{"d10", FIRST_VFP_REGNUM + 20, 2}, \
{"d11", FIRST_VFP_REGNUM + 22, 2}, \
{"d12", FIRST_VFP_REGNUM + 24, 2}, \
{"d13", FIRST_VFP_REGNUM + 26, 2}, \
{"d14", FIRST_VFP_REGNUM + 28, 2}, \
{"d15", FIRST_VFP_REGNUM + 30, 2}, \
{"q0", FIRST_VFP_REGNUM + 0, 4}, \
{"q1", FIRST_VFP_REGNUM + 4, 4}, \
{"q2", FIRST_VFP_REGNUM + 8, 4}, \
{"q3", FIRST_VFP_REGNUM + 12, 4}, \
{"q4", FIRST_VFP_REGNUM + 16, 4}, \
{"q5", FIRST_VFP_REGNUM + 20, 4}, \
{"q6", FIRST_VFP_REGNUM + 24, 4}, \
{"q7", FIRST_VFP_REGNUM + 28, 4}, \
{"q8", FIRST_VFP_REGNUM + 32, 4}, \
{"q9", FIRST_VFP_REGNUM + 36, 4}, \
{"q10", FIRST_VFP_REGNUM + 40, 4}, \
{"q11", FIRST_VFP_REGNUM + 44, 4}, \
{"q12", FIRST_VFP_REGNUM + 48, 4}, \
{"q13", FIRST_VFP_REGNUM + 52, 4}, \
{"q14", FIRST_VFP_REGNUM + 56, 4}, \
{"q15", FIRST_VFP_REGNUM + 60, 4} \
}
#endif
......
gcc/config/arm/arm-arches.def
......@@ -55,6 +55,5 @@ ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A)
ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R)
ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M)
ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM)
ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4)
ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)
ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
gcc/config/arm/arm-cores.def
......@@ -89,7 +89,7 @@ ARM_CORE("arm920", arm920, 4T, FL_LDSCHED, fastm
ARM_CORE("arm920t", arm920t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm922t", arm922t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm940t", arm940t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS, fastmul)
ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED, fastmul)
/* V5T Architecture Processors */
ARM_CORE("arm10tdmi", arm10tdmi, 5T, FL_LDSCHED, fastmul)
......
gcc/config/arm/arm-protos.h
......@@ -67,7 +67,6 @@ extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int);
extern bool ldm_stm_operation_p (rtx, bool, enum machine_mode mode,
bool, bool);
extern int arm_const_double_rtx (rtx);
extern int neg_const_double_rtx_ok_for_fpa (rtx);
extern int vfp3_const_double_rtx (rtx);
extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
......@@ -95,7 +94,6 @@ extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
bool);
extern bool arm_tls_referenced_p (rtx);
extern int cirrus_memory_offset (rtx);
extern int arm_coproc_mem_operand (rtx, bool);
extern int neon_vector_mem_operand (rtx, int);
extern int neon_struct_mem_operand (rtx);
......@@ -134,11 +132,7 @@ extern void arm_emit_call_insn (rtx, rtx);
extern const char *output_call (rtx *);
extern const char *output_call_mem (rtx *);
void arm_emit_movpair (rtx, rtx);
extern const char *output_mov_long_double_fpa_from_arm (rtx *);
extern const char *output_mov_long_double_arm_from_fpa (rtx *);
extern const char *output_mov_long_double_arm_from_arm (rtx *);
extern const char *output_mov_double_fpa_from_arm (rtx *);
extern const char *output_mov_double_arm_from_fpa (rtx *);
extern const char *output_move_double (rtx *, bool, int *count);
extern const char *output_move_quad (rtx *);
extern int arm_count_output_move_double_insns (rtx *);
......@@ -179,8 +173,6 @@ extern int arm_apply_result_size (void);
#endif /* RTX_CODE */
extern int arm_float_words_big_endian (void);
/* Thumb functions. */
extern void arm_init_expanders (void);
extern const char *thumb1_unexpanded_epilogue (void);
......
gcc/config/arm/arm-tables.opt
......@@ -347,13 +347,10 @@ EnumValue
Enum(arm_arch) String(armv7e-m) Value(22)
EnumValue
Enum(arm_arch) String(ep9312) Value(23)
Enum(arm_arch) String(iwmmxt) Value(23)
EnumValue
Enum(arm_arch) String(iwmmxt) Value(24)
EnumValue
Enum(arm_arch) String(iwmmxt2) Value(25)
Enum(arm_arch) String(iwmmxt2) Value(24)
Enum
Name(arm_fpu) Type(int)
......
gcc/config/arm/arm.md
......@@ -28,18 +28,17 @@
;;---------------------------------------------------------------------------
;; Constants
;; Register numbers
;; Register numbers -- All machine registers should be defined here
(define_constants
[(R0_REGNUM 0) ; First CORE register
(R1_REGNUM 1) ; Second CORE register
(IP_REGNUM 12) ; Scratch register
(SP_REGNUM 13) ; Stack pointer
(LR_REGNUM 14) ; Return address register
(PC_REGNUM 15) ; Program counter
(CC_REGNUM 24) ; Condition code pseudo register
(LAST_ARM_REGNUM 15) ;
(FPA_F0_REGNUM 16) ; FIRST_FPA_REGNUM
(FPA_F7_REGNUM 23) ; LAST_FPA_REGNUM
[(R0_REGNUM 0) ; First CORE register
(R1_REGNUM 1) ; Second CORE register
(IP_REGNUM 12) ; Scratch register
(SP_REGNUM 13) ; Stack pointer
(LR_REGNUM 14) ; Return address register
(PC_REGNUM 15) ; Program counter
(LAST_ARM_REGNUM 15) ;
(CC_REGNUM 100) ; Condition code pseudo register
(VFPCC_REGNUM 101) ; VFP Condition code pseudo register
]
)
;; 3rd operand to select_dominance_cc_mode
......@@ -178,7 +177,7 @@
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
; performance we should try and group them together).
(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
(define_attr "fpu" "none,vfp"
(const (symbol_ref "arm_fpu_attr")))
; LENGTH of an instruction (in bytes)
......
gcc/config/arm/linux-elf.h
......@@ -92,9 +92,8 @@
} \
while (0)
/* NWFPE always understands FPA instructions. */
#undef FPUTYPE_DEFAULT
#define FPUTYPE_DEFAULT "fpe3"
#define FPUTYPE_DEFAULT "vfp"
/* Call the function profiler with a given profile label. */
#undef ARM_FUNCTION_PROFILER
......
gcc/config/arm/vfp.md
......@@ -19,11 +19,6 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;; Additional register numbers
(define_constants
[(VFPCC_REGNUM 127)]
)
;; The VFP "type" attributes differ from those used in the FPA model.
;; fcpys Single precision cpy.
;; ffariths Single precision abs, neg.
......
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