The changes are made in the patch for optimized usage of fint instruction.

The sequence of fint/cond_branch is replaced with fcmp/cond_branch. The
fint instruction takes 6/7 cycles as compared to fcmp instruction which
takes 1 cycles. The conversion from float to int with fint instruction
is not required and can directly compared with fcmp instruction which
takes 1 cycle as compared to 6/7 cycles with fint instruction.

ChangeLog:
2015-03-04  Ajit Agarwal  <ajitkum@xilinx.com>

	* config/microblaze/microblaze.md (peephole2): New.

From-SVN: r222790

gcc/ChangeLog

+2015-05-04  Ajit Agarwal  <ajitkum@xilinx.com>
+
+	* config/microblaze/microblaze.md (peephole2): New.
+
 2015-05-04  Jeff Law  <law@redhat.com>
 
 	Revert:
 	2015-05-04  Jeff Law  <law@redhat.com>
 
-        * match.pd (bit_and (plus/minus (convert @0) (convert @1) mask): New
-        simplifier to narrow arithmetic.
-        * generic-match-head.c: (types_match, single_use): New functions.
-        * gimple-match-head.c: (types_match, single_use): New functions.
+	* match.pd (bit_and (plus/minus (convert @0) (convert @1) mask): New
+	simplifier to narrow arithmetic.
+	* generic-match-head.c: (types_match, single_use): New functions.
+	* gimple-match-head.c: (types_match, single_use): New functions.
 
 2015-05-04  Kaz Kojima  <kkojima@gcc.gnu.org>
 

gcc/config/microblaze/microblaze.md

@@ -663,6 +663,31 @@
   (set_attr "mode"	"SI")
   (set_attr "length"	"4")])
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand")
+        (fix:SI (match_operand:SF 1 "register_operand")))
+   (set (pc)
+        (if_then_else (match_operator 2 "ordered_comparison_operator"
+                       [(match_operand:SI 3 "register_operand")
+                        (match_operand:SI 4 "arith_operand")])
+                      (label_ref (match_operand 5))
+                      (pc)))]
+   "TARGET_HARD_FLOAT"
+   [(set (match_dup 1) (match_dup 3))]
+
+  {
+    rtx condition;
+    rtx cmp_op0 = operands[3];
+    rtx cmp_op1 = operands[4];
+    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+
+    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
+                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
+                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
+    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+    emit_jump_insn (gen_condjump (condition, operands[5]));
+  }
+)
 
 ;;----------------------------------------------------------------
 ;; Negation and one's complement