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riscv-gcc-1
Commit 0b871ccf by Yuri Rumyantsev Committed by Kirill Yukhin
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Silvermont (SLM) architecture pipeline model, tuning and insn selection. 

        Silvermont (SLM) architecture pipeline model, tuning and
        insn selection.
        * config.gcc: Add slm config options and target.

        * config/i386/slm.md: New.

        * config/i386/driver-i386.c (host_detect_local_cpu): Check movbe.

        * gcc/config/i386/i386-c.c (ix86_target_macros_internal):  New case
        PROCESSOR_SLM.
        (ix86_target_macros_internal): Likewise.

        * gcc/config/i386/i386.c (slm_cost): New cost.
        (m_SLM): New macro flag.
        (initial_ix86_tune_features): Set m_SLM.
        (x86_accumulate_outgoing_args): Likewise.
        (x86_arch_always_fancy_math_387): Likewise.
        (processor_target_table): Add slm cost.
        (cpu_names): Add slm cpu name.
        (x86_option_override_internal): Set SLM ISA.
        (ix86_issue_rate): New case PROCESSOR_SLM.
        (ia32_multipass_dfa_lookahead): Likewise.
        (fold_builtin_cpu): Add slm.

        * config/i386/i386.h (TARGET_SLM): New target macro.
        (target_cpu_default): Add TARGET_CPU_DEFAULT_slm.
        (processor_type): Add PROCESSOR_SLM.

        * config/i386/i386.md (cpu): Add new value "slm".
        (slm.md): Include slm.md.

        * libgcc/config/i386/cpuinfo.c (INTEL_SLM): New enum value.


Co-Authored-By: Igor Zamyatin <igor.zamyatin@intel.com>

From-SVN: r199444
parent 24d5b097
Showing with 72 additions and 10 deletions
gcc/ChangeLog
2013-05-30 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com>
Igor Zamyatin <igor.zamyatin@intel.com>
Silvermont (SLM) architecture pipeline model, tuning and
insn selection.
* config.gcc: Add slm config options and target.
* config/i386/slm.md: New.
* config/i386/driver-i386.c (host_detect_local_cpu): Check movbe.
* gcc/config/i386/i386-c.c (ix86_target_macros_internal): New case
PROCESSOR_SLM.
(ix86_target_macros_internal): Likewise.
* gcc/config/i386/i386.c (slm_cost): New cost.
(m_SLM): New macro flag.
(initial_ix86_tune_features): Set m_SLM.
(x86_accumulate_outgoing_args): Likewise.
(x86_arch_always_fancy_math_387): Likewise.
(processor_target_table): Add slm cost.
(cpu_names): Add slm cpu name.
(x86_option_override_internal): Set SLM ISA.
(ix86_issue_rate): New case PROCESSOR_SLM.
(ia32_multipass_dfa_lookahead): Likewise.
(fold_builtin_cpu): Add slm.
* config/i386/i386.h (TARGET_SLM): New target macro.
(target_cpu_default): Add TARGET_CPU_DEFAULT_slm.
(processor_type): Add PROCESSOR_SLM.
* config/i386/i386.md (cpu): Add new value "slm".
(slm.md): Include slm.md.
* libgcc/config/i386/cpuinfo.c (INTEL_SLM): New enum value.
2013-05-30 Bernd Schmidt <bernds@codesourcery.com>
Zhenqiang Chen <zhenqiang.chen@linaro.org>
......
gcc/config.gcc
......@@ -1293,7 +1293,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
need_64bit_isa=yes
case X"${with_cpu}" in
Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
;;
X)
if test x$with_cpu_64 = x; then
......@@ -1302,7 +1302,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
;;
*)
echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
echo "generic atom slm core2 corei7 corei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
exit 1
;;
esac
......@@ -1414,7 +1414,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
tmake_file="$tmake_file i386/t-sol2-64"
need_64bit_isa=yes
case X"${with_cpu}" in
Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
;;
X)
if test x$with_cpu_64 = x; then
......@@ -1423,7 +1423,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
;;
*)
echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
echo "generic atom slm core2 corei7 corei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
exit 1
;;
esac
......@@ -1496,7 +1496,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
if test x$enable_targets = xall; then
tm_defines="${tm_defines} TARGET_BI_ARCH=1"
case X"${with_cpu}" in
Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
;;
X)
if test x$with_cpu_64 = x; then
......@@ -1505,7 +1505,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
;;
*)
echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
echo "generic atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
exit 1
;;
esac
......@@ -2848,6 +2848,10 @@ case ${target} in
arch=atom
cpu=atom
;;
slm-*)
arch=slm
cpu=slm
;;
core2-*)
arch=core2
cpu=core2
......@@ -2919,6 +2923,10 @@ case ${target} in
arch=atom
cpu=atom
;;
slm-*)
arch=slm
cpu=slm
;;
core2-*)
arch=core2
cpu=core2
......@@ -3422,7 +3430,7 @@ case "${target}" in
| k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \
| opteron-sse3 | athlon-fx | bdver3 | bdver2 | bdver1 | btver2 \
| btver1 | amdfam10 | barcelona | nocona | core2 | corei7 \
| corei7-avx | core-avx-i | core-avx2 | atom)
| corei7-avx | core-avx-i | core-avx2 | atom | slm)
# OK
;;
*)
......
gcc/config/i386/driver-i386.c
......@@ -674,8 +674,14 @@ const char *host_detect_local_cpu (int argc, const char **argv)
/* Assume Sandy Bridge. */
cpu = "corei7-avx";
else if (has_sse4_2)
/* Assume Core i7. */
cpu = "corei7";
{
if (has_movbe)
/* Assume SLM. */
cpu = "slm";
else
/* Assume Core i7. */
cpu = "corei7";
}
else if (has_ssse3)
{
if (has_movbe)
......
gcc/config/i386/i386-c.c
......@@ -149,6 +149,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__atom");
def_or_undef (parse_in, "__atom__");
break;
case PROCESSOR_SLM:
def_or_undef (parse_in, "__slm");
def_or_undef (parse_in, "__slm__");
break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
......@@ -241,6 +245,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_ATOM:
def_or_undef (parse_in, "__tune_atom__");
break;
case PROCESSOR_SLM:
def_or_undef (parse_in, "__tune_slm__");
break;
case PROCESSOR_GENERIC32:
case PROCESSOR_GENERIC64:
break;
......
gcc/config/i386/i386.h
......@@ -257,6 +257,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
#define TARGET_SLM (ix86_tune == PROCESSOR_SLM)
/* Feature tests against the various tunings. */
enum ix86_tune_indices {
......@@ -623,6 +624,7 @@ enum target_cpu_default
TARGET_CPU_DEFAULT_corei7,
TARGET_CPU_DEFAULT_haswell,
TARGET_CPU_DEFAULT_atom,
TARGET_CPU_DEFAULT_slm,
TARGET_CPU_DEFAULT_geode,
TARGET_CPU_DEFAULT_k6,
......@@ -2131,6 +2133,7 @@ enum processor_type
PROCESSOR_BTVER1,
PROCESSOR_BTVER2,
PROCESSOR_ATOM,
PROCESSOR_SLM,
PROCESSOR_max
};
......
gcc/config/i386/i386.md
......@@ -323,7 +323,7 @@
;; Processor type.
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
atom,generic64,amdfam10,bdver1,bdver2,bdver3,btver1,btver2"
atom,slm,generic64,amdfam10,bdver1,bdver2,bdver3,btver1,btver2"
(const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be
......@@ -964,6 +964,7 @@
(include "btver2.md")
(include "geode.md")
(include "atom.md")
(include "slm.md")
(include "core2.md")
......
libgcc/config/i386/cpuinfo.c
......@@ -50,6 +50,7 @@ enum processor_vendor
enum processor_types
{
INTEL_ATOM = 1,
INTEL_SLM,
INTEL_CORE2,
INTEL_COREI7,
AMDFAM10H,
......
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