[AArch64]Add vec_shr pattern for 64-bit vectors using ush{l,r}; enable tests.

gcc/:
 
	* config/aarch64/aarch64-simd.md (vec_shr<mode>): New.

gcc/testsuite/:

	* lib/target-supports.exp (check_effective_target_whole_vector_shift):
	Add aarch64{,_be}.

From-SVN: r218022

gcc/ChangeLog

 2014-11-24  Alan Lawrence  <alan.lawrence@arm.com>
 
+	* config/aarch64/aarch64-simd.md (vec_shr<mode>): New.
+
+2014-11-24  Alan Lawrence  <alan.lawrence@arm.com>
+
 	* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):
 	Refactor by combining switch statements and make arrays into scalars.
 

gcc/config/aarch64/aarch64-simd.md

@@ -795,6 +795,21 @@
   }
 )
 
+;; For 64-bit modes we use ushl/r, as this does not require a SIMD zero.
+(define_insn "vec_shr_<mode>"
+  [(set (match_operand:VD 0 "register_operand" "=w")
+        (lshiftrt:VD (match_operand:VD 1 "register_operand" "w")
+		     (match_operand:SI 2 "immediate_operand" "i")))]
+  "TARGET_SIMD"
+  {
+    if (BYTES_BIG_ENDIAN)
+      return "ushl %d0, %d1, %2";
+    else
+      return "ushr %d0, %d1, %2";
+  }
+  [(set_attr "type" "neon_shift_imm")]
+)
+
 (define_insn "aarch64_simd_vec_setv2di"
   [(set (match_operand:V2DI 0 "register_operand" "=w,w")
         (vec_merge:V2DI

gcc/testsuite/ChangeLog

+2014-11-24  Alan Lawrence  <alan.lawrence@arm.com>
+
+        * lib/target-supports.exp (check_effective_target_whole_vector_shift):
+	Add aarch64{,_be}.
+
 2014-11-24  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/63679

gcc/testsuite/lib/target-supports.exp

@@ -3399,6 +3399,7 @@ proc check_effective_target_vect_shift { } {
 proc check_effective_target_whole_vector_shift { } {
     if { [istarget i?86-*-*] || [istarget x86_64-*-*]
 	 || [istarget ia64-*-*]
+	 || [istarget aarch64*-*-*]
 	 || ([check_effective_target_arm32]
 	     && [check_effective_target_arm_little_endian])
 	 || ([istarget mips*-*-*]