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lvzhengyang
riscv-gcc-1
Commits
0b4ce21b
Commit
0b4ce21b
authored
Mar 04, 2013
by
Georg-Johann Lay
Committed by
Georg-Johann Lay
Mar 04, 2013
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* config/avr/lib1funcs.S (__ashrdi3, __lshrdi3, __ashldi3)
(__rotldi3): Shift bytewise if applicable. From-SVN: r196431
parent
2f4e77e8
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libgcc/ChangeLog
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0b4ce21b
2013-03-04 Georg-Johann Lay <avr@gjlay.de>
* config/avr/lib1funcs.S (__ashrdi3, __lshrdi3, __ashldi3)
(__rotldi3): Shift bytewise if applicable.
2013-03-01 James Greenhalgh <james.greenhalgh@arm.com>
2013-03-01 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/sync-cache.c
* config/aarch64/sync-cache.c
...
...
libgcc/config/avr/lib1funcs.S
View file @
0b4ce21b
...
@@ -3030,64 +3030,73 @@ ENDF __bswapdi2
...
@@ -3030,64 +3030,73 @@ ENDF __bswapdi2
;; Arithmetic shift right
;; Arithmetic shift right
;; r25:r18 = ashr64 (r25:r18, r17:r16)
;; r25:r18 = ashr64 (r25:r18, r17:r16)
DEFUN __ashrdi3
DEFUN __ashrdi3
push r16
bst r25, 7
andi r16, 63
bld __zero_reg__, 0
breq 2f
;; FALLTHRU
1: asr r25
ENDF __ashrdi3
ror r24
ror r23
ror r22
ror r21
ror r20
ror r19
ror r18
dec r16
brne 1b
2: pop r16
ret
ENDF __ashrdi3
#endif /* defined (L_ashrdi3) */
#if defined (L_lshrdi3)
;; Logic shift right
;; Logic shift right
;; r25:r18 = lshr64 (r25:r18, r17:r16)
;; r25:r18 = lshr64 (r25:r18, r17:r16)
DEFUN __lshrdi3
DEFUN __lshrdi3
push r16
lsr __zero_reg__
andi r16, 63
sbc __tmp_reg__, __tmp_reg__
breq 2f
push r16
1: lsr r25
0: cpi r16, 8
ror r24
brlo 2f
ror r23
subi r16, 8
ror r22
mov r18, r19
ror r21
mov r19, r20
ror r20
mov r20, r21
ror r19
mov r21, r22
ror r18
mov r22, r23
dec r16
mov r23, r24
brne 1b
mov r24, r25
2: pop r16
mov r25, __tmp_reg__
rjmp 0b
1: asr __tmp_reg__
ror r25
ror r24
ror r23
ror r22
ror r21
ror r20
ror r19
ror r18
2: dec r16
brpl 1b
pop r16
ret
ret
ENDF __lshrdi3
ENDF __lshrdi3
#endif /* defined (L_
l
shrdi3) */
#endif /* defined (L_
a
shrdi3) */
#if defined (L_ashldi3)
#if defined (L_ashldi3)
;; Shift left
;; Shift left
;; r25:r18 = ashl64 (r25:r18, r17:r16)
;; r25:r18 = ashl64 (r25:r18, r17:r16)
DEFUN __ashldi3
DEFUN __ashldi3
push r16
push r16
andi r16, 63
0: cpi r16, 8
breq 2f
brlo 2f
1: lsl r18
mov r25, r24
rol r19
mov r24, r23
rol r20
mov r23, r22
rol r21
mov r22, r21
rol r22
mov r21, r20
rol r23
mov r20, r19
rol r24
mov r19, r18
rol r25
clr r18
dec r16
subi r16, 8
brne 1b
rjmp 0b
2: pop r16
1: lsl r18
rol r19
rol r20
rol r21
rol r22
rol r23
rol r24
rol r25
2: dec r16
brpl 1b
pop r16
ret
ret
ENDF __ashldi3
ENDF __ashldi3
#endif /* defined (L_ashldi3) */
#endif /* defined (L_ashldi3) */
...
@@ -3096,21 +3105,32 @@ ENDF __ashldi3
...
@@ -3096,21 +3105,32 @@ ENDF __ashldi3
;; Shift left
;; Shift left
;; r25:r18 = rotl64 (r25:r18, r17:r16)
;; r25:r18 = rotl64 (r25:r18, r17:r16)
DEFUN __rotldi3
DEFUN __rotldi3
push r16
push r16
andi r16, 63
0: cpi r16, 8
breq 2f
brlo 2f
1: lsl r18
subi r16, 8
rol r19
mov __tmp_reg__, r25
rol r20
mov r25, r24
rol r21
mov r24, r23
rol r22
mov r23, r22
rol r23
mov r22, r21
rol r24
mov r21, r20
rol r25
mov r20, r19
adc r18, __zero_reg__
mov r19, r18
dec r16
mov r18, __tmp_reg__
brne 1b
rjmp 0b
2: pop r16
1: lsl r18
rol r19
rol r20
rol r21
rol r22
rol r23
rol r24
rol r25
adc r18, __zero_reg__
2: dec r16
brpl 1b
pop r16
ret
ret
ENDF __rotldi3
ENDF __rotldi3
#endif /* defined (L_rotldi3) */
#endif /* defined (L_rotldi3) */
...
...
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