* config/frv/frv-protos.h (frv_branch_cost_string, frv_branch_cost_int)

	(frv_cpu_string, frv_condexec_insns_str, frv_condexec_insns)
	(frv_condexec_temps_str, frv_condexec_temps, frv_sched_lookahead_str)
	(frv_sched_lookahead): Delete.
	* config/frv/frv.h (MASK_DEFAULT_ALLOC_CC): Move to frv.c.
	(target_flags, MASK_GPR_32, MASK_FPR_32, MASK_SOFT_FLOAT)
	(MASK_ALLOC_CC, MASK_DWORD, MASK_DOUBLE, MASK_MEDIA, MASK_MULADD)
	(MASK_LIBPIC, MASK_ACC_4,  MASK_PACK, MASK_LONG_CALLS)
	(MASK_ALIGN_LABELS, MASK_LINKED_FP, MASK_BIG_TLS, MASK_DEBUG_ARG)
	(MASK_DEBUG_ADDR, MASK_DEBUG_STACK, MASK_DEBUG, MASK_DEBUG_LOC)
	(MASK_DEBUG_COND_EXEC, MASK_NO_COND_MOVE, MASK_NO_SCC)
	(MASK_NO_COND_EXEC, MASK_NO_VLIW_BRANCH, MASK_NO_MULTI_CE)
	(MASK_FDPIC, MASK_INLINE_PLT, MASK_GPREL_RO, MASK_DEFAULT)
	(TARGET_GPR_32, TARGET_FPR_32, TARGET_SOFT_FLOAT, TARGET_ALLOC_CC)
	(TARGET_DWORD, TARGET_DOUBLE, TARGET_MEDIA, TARGET_MULADD)
	(TARGET_LIBPIC, TARGET_ACC_4, TARGET_DEBUG_ARG, TARGET_DEBUG_ADDR)
	(TARGET_DEBUG_STACK, TARGET_DEBUG, TARGET_DEBUG_LOC)
	(TARGET_DEBUG_COND_EXEC, TARGET_NO_COND_MOVE, TARGET_NO_SCC)
	(TARGET_NO_COND_EXEC, TARGET_NO_VLIW_BRANCH, TARGET_NO_MULTI_CE)
	(TARGET_NO_NESTED_CE, TARGET_FDPIC, TARGET_INLINE_PLT, TARGET_BIG_TLS)
	(TARGET_GPREL_RO, TARGET_PACK, TARGET_LONG_CALLS, TARGET_ALIGN_LABELS)
	(TARGET_LINKED_FP, TARGET_GPR_64, TARGET_FPR_64, TARGET_HARD_FLOAT)
	(TARGET_FIXED_CC, TARGET_COND_MOVE, TARGET_SCC, TARGET_COND_EXEC)
	(TARGET_VLIW_BRANCH, TARGET_MULTI_CE, TARGET_NESTED_CE, TARGET_ACC_8)
	(TARGET_SWITCHES, TARGET_OPTIONS, DEFAULT_CONDEXEC_TEMPS)
	(DEFAULT_BRANCH_COST, DEFAULT_CONDEXEC_INSNS): Delete.
	* config/frv/frv.c (frv_branch_cost_string, frv_branch_cost_int)
	(frv_cpu_string, frv_condexec_insns_str, frv_condexec_insns)
	(frv_condexec_temps_str, frv_condexec_temps, frv_sched_lookahead_str)
	(frv_sched_lookahead): Delete.
	(MASK_DEFAULT_ALLOC_CC): Moved from frv.h.
	(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
	(frv_handle_option): New function.  Move -mcpu= handling from...
	(frv_override_options): ...here.  Remove handling of other
	TARGET_OPTIONS.
	(frv_ifcvt_modify_tests): Check !TARGET_COND_EXEC instead of
	TARGET_NO_COND_EXEC and !TARGET_NESTED_CE to TARGET_NO_NESTED_CE.
	(frv_ifcvt_modify_multiple_tests): Likewise !TARGET_MULTI_CE
	and TARGET_NO_MULTI_CE.
	(frv_for_each_packet): Likewise TARGET_NO_VLIW_BRANCH and
	!TARGET_VLIW_BRANCH.
	* config/frv/frv.opt: New file.

From-SVN: r96883

gcc/ChangeLog

+2005-03-22  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/frv/frv-protos.h (frv_branch_cost_string, frv_branch_cost_int)
+	(frv_cpu_string, frv_condexec_insns_str, frv_condexec_insns)
+	(frv_condexec_temps_str, frv_condexec_temps, frv_sched_lookahead_str)
+	(frv_sched_lookahead): Delete.
+	* config/frv/frv.h (MASK_DEFAULT_ALLOC_CC): Move to frv.c.
+	(target_flags, MASK_GPR_32, MASK_FPR_32, MASK_SOFT_FLOAT)
+	(MASK_ALLOC_CC, MASK_DWORD, MASK_DOUBLE, MASK_MEDIA, MASK_MULADD)
+	(MASK_LIBPIC, MASK_ACC_4,  MASK_PACK, MASK_LONG_CALLS)
+	(MASK_ALIGN_LABELS, MASK_LINKED_FP, MASK_BIG_TLS, MASK_DEBUG_ARG)
+	(MASK_DEBUG_ADDR, MASK_DEBUG_STACK, MASK_DEBUG, MASK_DEBUG_LOC)
+	(MASK_DEBUG_COND_EXEC, MASK_NO_COND_MOVE, MASK_NO_SCC)
+	(MASK_NO_COND_EXEC, MASK_NO_VLIW_BRANCH, MASK_NO_MULTI_CE)
+	(MASK_FDPIC, MASK_INLINE_PLT, MASK_GPREL_RO, MASK_DEFAULT)
+	(TARGET_GPR_32, TARGET_FPR_32, TARGET_SOFT_FLOAT, TARGET_ALLOC_CC)
+	(TARGET_DWORD, TARGET_DOUBLE, TARGET_MEDIA, TARGET_MULADD)
+	(TARGET_LIBPIC, TARGET_ACC_4, TARGET_DEBUG_ARG, TARGET_DEBUG_ADDR)
+	(TARGET_DEBUG_STACK, TARGET_DEBUG, TARGET_DEBUG_LOC)
+	(TARGET_DEBUG_COND_EXEC, TARGET_NO_COND_MOVE, TARGET_NO_SCC)
+	(TARGET_NO_COND_EXEC, TARGET_NO_VLIW_BRANCH, TARGET_NO_MULTI_CE)
+	(TARGET_NO_NESTED_CE, TARGET_FDPIC, TARGET_INLINE_PLT, TARGET_BIG_TLS)
+	(TARGET_GPREL_RO, TARGET_PACK, TARGET_LONG_CALLS, TARGET_ALIGN_LABELS)
+	(TARGET_LINKED_FP, TARGET_GPR_64, TARGET_FPR_64, TARGET_HARD_FLOAT)
+	(TARGET_FIXED_CC, TARGET_COND_MOVE, TARGET_SCC, TARGET_COND_EXEC)
+	(TARGET_VLIW_BRANCH, TARGET_MULTI_CE, TARGET_NESTED_CE, TARGET_ACC_8)
+	(TARGET_SWITCHES, TARGET_OPTIONS, DEFAULT_CONDEXEC_TEMPS)
+	(DEFAULT_BRANCH_COST, DEFAULT_CONDEXEC_INSNS): Delete.
+	* config/frv/frv.c (frv_branch_cost_string, frv_branch_cost_int)
+	(frv_cpu_string, frv_condexec_insns_str, frv_condexec_insns)
+	(frv_condexec_temps_str, frv_condexec_temps, frv_sched_lookahead_str)
+	(frv_sched_lookahead): Delete.
+	(MASK_DEFAULT_ALLOC_CC): Moved from frv.h.
+	(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
+	(frv_handle_option): New function.  Move -mcpu= handling from...
+	(frv_override_options): ...here.  Remove handling of other
+	TARGET_OPTIONS.
+	(frv_ifcvt_modify_tests): Check !TARGET_COND_EXEC instead of
+	TARGET_NO_COND_EXEC and !TARGET_NESTED_CE to TARGET_NO_NESTED_CE.
+	(frv_ifcvt_modify_multiple_tests): Likewise !TARGET_MULTI_CE
+	and TARGET_NO_MULTI_CE.
+	(frv_for_each_packet): Likewise TARGET_NO_VLIW_BRANCH and
+	!TARGET_VLIW_BRANCH.
+	* config/frv/frv.opt: New file.
+
 2005-03-22  Kazu Hirata  <kazu@cs.umass.edu>
 
 	* fold-const.c (fold_ternary): Take decomposed arguments of

gcc/config/frv/frv-protos.h

@@ -20,25 +20,6 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-/* Define global data defined in frv.c.  */
-extern const char *frv_branch_cost_string;	/* -mbranch-cost option */
-extern int frv_branch_cost_int;			/* value of -mbranch_cost */
-
-extern const char *frv_cpu_string;		/* -mcpu= option */
-
-extern const char *frv_condexec_insns_str;	/* -mcond-exec-insns= option */
-extern int frv_condexec_insns;			/* value of -mcond-exec-insns */
-
-extern const char *frv_condexec_temps_str;	/* -mcond-exec-temps= option */
-extern int frv_condexec_temps;			/* value of -mcond-exec-temps */
-
-extern const char *frv_sched_lookahead_str;	/* -msched-lookahead= option */
-extern int frv_sched_lookahead;			/* value -msched-lookahead= */
-
 /* CPU type.  This must be identical to the cpu enumeration in frv.md.  */
 typedef enum frv_cpu
 {

gcc/config/frv/frv.c

@@ -247,27 +247,12 @@ enum reg_class reg_class_from_letter[256];
 /* Cached value of frv_stack_info.  */
 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
 
-/* -mbranch-cost= support */
-const char *frv_branch_cost_string;
-int frv_branch_cost_int = DEFAULT_BRANCH_COST;
-
 /* -mcpu= support */
-const char *frv_cpu_string;		/* -mcpu= option */
 frv_cpu_t frv_cpu_type = CPU_TYPE;	/* value of -mcpu= */
 
-/* -mcond-exec-insns= support */
-const char *frv_condexec_insns_str;		 /* -mcond-exec-insns= option */
-int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
-
-/* -mcond-exec-temps= support */
-const char *frv_condexec_temps_str;		 /* -mcond-exec-temps= option */
-int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
-
-/* -msched-lookahead=n */
-const char *frv_sched_lookahead_str;	 /* -msched-lookahead=n */
-int frv_sched_lookahead = 4;		 /* -msched-lookahead=n */
-
 /* Forward references */
+
+static bool frv_handle_option			(size_t, const char *, int);
 static int frv_default_flags_for_cpu		(void);
 static int frv_string_begins_with		(tree, const char *);
 static FRV_INLINE bool frv_small_data_reloc_p	(rtx, int);
@@ -380,6 +365,13 @@ static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
 				  tree, bool);
 
+/* Allow us to easily change the default for -malloc-cc.  */
+#ifndef DEFAULT_NO_ALLOC_CC
+#define MASK_DEFAULT_ALLOC_CC	MASK_ALLOC_CC
+#else
+#define MASK_DEFAULT_ALLOC_CC	0
+#endif
+
 /* Initialize the GCC target structure.  */
 #undef  TARGET_ASM_FUNCTION_PROLOGUE
 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
@@ -387,6 +379,17 @@ static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
 #undef  TARGET_ASM_INTEGER
 #define TARGET_ASM_INTEGER frv_assemble_integer
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS		\
+  (MASK_DEFAULT_ALLOC_CC			\
+   | MASK_COND_MOVE				\
+   | MASK_SCC					\
+   | MASK_COND_EXEC				\
+   | MASK_VLIW_BRANCH				\
+   | MASK_MULTI_CE				\
+   | MASK_NESTED_CE)
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION frv_handle_option
 #undef TARGET_INIT_BUILTINS
 #define TARGET_INIT_BUILTINS frv_init_builtins
 #undef TARGET_EXPAND_BUILTIN
@@ -519,6 +522,41 @@ frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
   return TARGET_FDPIC;
 }
 
+/* Implement TARGET_HANDLE_OPTION.  */
+
+static bool
+frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+{
+  switch (code)
+    {
+    case OPT_mcpu_:
+      if (strcmp (arg, "simple") == 0)
+	frv_cpu_type = FRV_CPU_SIMPLE;
+      else if (strcmp (arg, "tomcat") == 0)
+	frv_cpu_type = FRV_CPU_TOMCAT;
+      else if (strcmp (arg, "fr550") == 0)
+	frv_cpu_type = FRV_CPU_FR550;
+      else if (strcmp (arg, "fr500") == 0)
+	frv_cpu_type = FRV_CPU_FR500;
+      else if (strcmp (arg, "fr450") == 0)
+	frv_cpu_type = FRV_CPU_FR450;
+      else if (strcmp (arg, "fr405") == 0)
+	frv_cpu_type = FRV_CPU_FR405;
+      else if (strcmp (arg, "fr400") == 0)
+	frv_cpu_type = FRV_CPU_FR400;
+      else if (strcmp (arg, "fr300") == 0)
+	frv_cpu_type = FRV_CPU_FR300;
+      else if (strcmp (arg, "frv") == 0)
+	frv_cpu_type = FRV_CPU_GENERIC;
+      else
+	return false;
+      return true;
+
+    default:
+      return true;
+    }
+}
+
 static int
 frv_default_flags_for_cpu (void)
 {
@@ -563,47 +601,6 @@ frv_override_options (void)
   int regno;
   unsigned int i;
 
-  /* Set the cpu type.  */
-  if (frv_cpu_string)
-    {
-      if (strcmp (frv_cpu_string, "simple") == 0)
-	frv_cpu_type = FRV_CPU_SIMPLE;
-
-      else if (strcmp (frv_cpu_string, "tomcat") == 0)
-	frv_cpu_type = FRV_CPU_TOMCAT;
-
-      else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
-	error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
-
-      else
-	{
-	  const char *p = frv_cpu_string + sizeof ("fr") - 1;
-	  if (strcmp (p, "550") == 0)
-	    frv_cpu_type = FRV_CPU_FR550;
-
-	  else if (strcmp (p, "500") == 0)
-	    frv_cpu_type = FRV_CPU_FR500;
-
-	  else if (strcmp (p, "450") == 0)
-	    frv_cpu_type = FRV_CPU_FR450;
-
-	  else if (strcmp (p, "405") == 0)
-	    frv_cpu_type = FRV_CPU_FR405;
-
-	  else if (strcmp (p, "400") == 0)
-	    frv_cpu_type = FRV_CPU_FR400;
-
-	  else if (strcmp (p, "300") == 0)
-	    frv_cpu_type = FRV_CPU_FR300;
-
-	  else if (strcmp (p, "v") == 0)
-	    frv_cpu_type = FRV_CPU_GENERIC;
-
-	  else
-	    error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
-	}
-    }
-
   target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
 
   /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
@@ -620,22 +617,6 @@ frv_override_options (void)
 	}
     }
 
-  /* Change the branch cost value.  */
-  if (frv_branch_cost_string)
-    frv_branch_cost_int = atoi (frv_branch_cost_string);
-
-  /* Change the # of insns to be converted to conditional execution.  */
-  if (frv_condexec_insns_str)
-    frv_condexec_insns = atoi (frv_condexec_insns_str);
-
-  /* Change # of temporary registers used to hold integer constants.  */
-  if (frv_condexec_temps_str)
-    frv_condexec_temps = atoi (frv_condexec_temps_str);
-
-  /* Change scheduling look ahead.  */
-  if (frv_sched_lookahead_str)
-    frv_sched_lookahead = atoi (frv_sched_lookahead_str);
-
   /* A C expression whose value is a register class containing hard
      register REGNO.  In general there is more than one such class;
      choose a class which is "minimal", meaning that no smaller class
@@ -6793,8 +6774,8 @@ frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
   /* Make sure we are only dealing with hard registers.  Also honor the
      -mno-cond-exec switch, and -mno-nested-cond-exec switches if
      applicable.  */
-  if (!reload_completed || TARGET_NO_COND_EXEC
-      || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
+  if (!reload_completed || !TARGET_COND_EXEC
+      || (!TARGET_NESTED_CE && ce_info->pass > 1))
     goto fail;
 
   /* Figure out which registers we can allocate for our own purposes.  Only
@@ -7153,7 +7134,7 @@ frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
       debug_rtx (*p_false);
     }
 
-  if (TARGET_NO_MULTI_CE)
+  if (!TARGET_MULTI_CE)
     goto fail;
 
   if (GET_CODE (cr) != REG)
@@ -8920,7 +8901,7 @@ frv_for_each_packet (void (*handle_packet) (void))
   /* Early exit if we don't want to pack insns.  */
   if (!optimize
       || !flag_schedule_insns_after_reload
-      || TARGET_NO_VLIW_BRANCH
+      || !TARGET_VLIW_BRANCH
       || frv_packet.issue_rate == 1)
     return false;
 

gcc/config/frv/frv.opt

+; Options for the FR-V port of the compiler.
+
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+macc-4
+Target Report RejectNegative Mask(ACC_4)
+Use 4 media accumulators
+
+macc-8
+Target Report RejectNegative InverseMask(ACC_4, ACC_8)
+Use 8 media accumulators
+
+malign-labels
+Target Report Mask(ALIGN_LABELS)
+Enable label alignment optimizations
+
+malloc-cc
+Target Report RejectNegative Mask(ALLOC_CC)
+Dynamically allocate cc registers
+
+; We used to default the branch cost to 2, but it was changed it to 1 to avoid
+; generating SCC instructions and or/and-ing them together, and then doing the
+; branch on the result, which collectively generate much worse code.
+mbranch-cost=
+Target RejectNegative Joined UInteger Var(frv_branch_cost_int) Init(1)
+Set the cost of branches
+
+mcond-exec
+Target Report Mask(COND_EXEC)
+Enable conditional execution other than moves/scc
+
+mcond-exec-insns=
+Target RejectNegative Joined UInteger Var(frv_condexec_insns) Init(8)
+Change the maximum length of conditionally-executed sequences
+
+mcond-exec-temps=
+Target RejectNegative Joined UInteger Var(frv_condexec_temps) Init(4)
+Change the number of temporary registers that are available to conditionally-executed sequences
+
+mcond-move
+Target Report Mask(COND_MOVE)
+Enable conditional moves
+
+mcpu=
+Target RejectNegative Joined
+Set the target CPU type
+
+mdebug
+Target Undocumented Var(TARGET_DEBUG)
+
+mdebug-arg
+Target Undocumented Var(TARGET_DEBUG_ARG)
+
+mdebug-addr
+Target Undocumented Var(TARGET_DEBUG_ADDR)
+
+mdebug-cond-exec
+Target Undocumented Var(TARGET_DEBUG_COND_EXEC)
+
+mdebug-loc
+Target Undocumented Var(TARGET_DEBUG_LOC)
+
+mdebug-stack
+Target Undocumented Var(TARGET_DEBUG_STACK)
+
+mdouble
+Target Report Mask(DOUBLE)
+Use fp double instructions
+
+mdword
+Target Report Mask(DWORD)
+Change the ABI to allow double word insns
+
+mfdpic
+Target Report Mask(FDPIC)
+Enable Function Descriptor PIC mode
+
+mfixed-cc
+Target Report RejectNegative InverseMask(ALLOC_CC, FIXED_CC)
+Just use icc0/fcc0
+
+mfpr-32
+Target Report RejectNegative Mask(FPR_32)
+Only use 32 FPRs
+
+mfpr-64
+Target Report RejectNegative InverseMask(FPR_32, FPR_64)
+Use 64 FPRs
+
+mgpr-32
+Target Report RejectNegative Mask(GPR_32)
+Only use 32 GPRs
+
+mgpr-64
+Target Report RejectNegative InverseMask(GPR_32, GPR_64)
+Use 64 GPRs
+
+mgprel-ro
+Target Report Mask(GPREL_RO)
+Enable use of GPREL for read-only data in FDPIC
+
+mhard-float
+Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
+Use hardware floating point
+
+minline-plt
+Target Report Mask(INLINE_PLT)
+Enable inlining of PLT in function calls
+
+mlibrary-pic
+Target Report Mask(LIBPIC)
+Enable PIC support for building libraries
+
+mlinked-fp
+Target Report Mask(LINKED_FP)
+Follow the EABI linkage requirements
+
+mlong-calls
+Target Report Mask(LONG_CALLS)
+Disallow direct calls to global functions
+
+mmedia
+Target Report Mask(MEDIA)
+Use media instructions
+
+mmuladd
+Target Report Mask(MULADD)
+Use multiply add/subtract instructions
+
+mmulti-cond-exec
+Target Report Mask(MULTI_CE)
+Enable optimizing &&/|| in conditional execution
+
+mnested-cond-exec
+Target Report Mask(NESTED_CE)
+Enable nested conditional execution optimizations
+
+; Not used by the compiler proper.
+mno-eflags
+Target RejectNegative
+Do not mark ABI switches in e_flags
+
+mpack
+Target Report Mask(PACK)
+Pack VLIW instructions
+
+mscc
+Target Report Mask(SCC)
+Enable setting GPRs to the result of comparisons
+
+msched-lookahead=
+Target RejectNegative Joined UInteger Var(frv_sched_lookahead) Init(4)
+Change the amount of scheduler lookahead
+
+msoft-float
+Target Report RejectNegative Mask(SOFT_FLOAT)
+Use software floating point
+
+mTLS
+Target Report RejectNegative Mask(BIG_TLS)
+Assume a large TLS segment
+
+mtls
+Target Report RejectNegative InverseMask(BIG_TLS)
+Do not assume a large TLS segment
+
+; Not used by the compiler proper.
+mtomcat-stats
+Target
+Cause gas to print tomcat statistics
+
+; Not used by the compiler proper.
+multilib-library-pic
+Target RejectNegative
+Link with the library-pic libraries
+
+mvliw-branch
+Target Report Mask(VLIW_BRANCH)
+Allow branches to be packed with other instructions