Commit 0ac78517 by J"orn Rennecke Committed by Joern Rennecke

sh-protos.h (binary_float_operator): Remove declaration.

	* sh-protos.h (binary_float_operator): Remove declaration.
	(sh_expand_unop_v2sf, sh_expand_binop_v2sf): Declare.
	* sh.c (print_operand, case 'N'): Check against CONST0_RTX.
	(unary_float_operator, sh_expand_unop_v2sf): New functions.
	(sh_expand_binop_v2sf): Likewise.
	(zero_vec_operand): Delete.
	(SH_BLTIN_UDI): New builtin shared signature define.  Renumbered
	all non-shared ones.
	(bdesc): Change all the mextr builtins to use SH_BLTIN_UDI.
	Enable nsb and byterev.
	* sh.h (CONDITIONAL_REGISTER_USAGE): Initialize DF_HI_REGS.
	(HARD_REGNO_MODE_OK): Allow TImode in fp regs.  Allow V2SFmode
	in general regs.
	(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add DF_HI_REGS.
	(SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.  Remove clause for
	immediate operands.
	(SECONDARY_INPUT_RELOAD_CLASS): Add clause for immediate operands.
	Add DF_HI_REGS.
	(CLASS_CANNOT_CHANGE_MODE, CLASS_CANNOT_CHANGE_MODE_P): Allow
	lowpart fp regs - only for big endian for now.
	(LEGITIMATE_CONSTANT_P): Don't allow non-zero float vectors
	when FPU is in use.
	(EXTRA_CONTRAINT_U): Check against CONST0_RTX.
	(LOAD_EXTEND_OP): NIL for SImode.
	(REGISTER_MOVE_COST): Add DF_HI_REGS.  Const for moves between
	general and fp registers is 4.
	PREDICATE_CODES: Amend binary_float_operator entry.
	Remove zero_vec_operand.  Add unary_float_operator.
	* sh.md (udivsi3_i4_media): Use truncate instead of paradoxical
	subreg SET_DEST.
	(truncdisi2, truncdihi2, movv2sf): Allow memory destinations.
	(truncdiqi2): Do sign extension.
	(movsi_media, movdi_media): Allow to use r63 to an fp register.
	(movdf_media, movsf_media): Likewise.
	(movv2sf_i, movv2sf_i+1): Don't use f{ld,st}.p or SUBREGS.
	Collapse to one define_insn_and_split.  Allow immediate sources.
	(addv2sf3, subv2sf3, mulv2sf3, divv2sf3): New patterns.
	(movv4sf_i): Allow immediate sources.  Use simplify_gen_subreg.
	(movv4sf): Allow immediate sources.
	(movsf_media_nofpu+1): Don't split moves to FP registers.
	(unary_sf_op, binary_sf_op, mshflo_w_x, concat_v2sf): New patterns.
	(movv8qi_i+3): Check against CONST0_RTX.
	(mextr1, mextr2. mextr3. mextr4, mextr5, mextr6, mextr7): Use DImode
	for input and output operands.  Fix argument 3 to gen_mextr_rl.
	(mmul23_wl, mmul01_wl, mmulsum_wq_i): s/const_vector/parallel/
	(msad_ubq_i, mshf4_b, mshf0_b, mshf4_l, mshf0_l, mshf4_w): Likewise.
	(mshf0_w, fipr, ftrv): Likewise.
	(mshfhi_l_di): Now insn_and_split.  Can handle FP regs.

From-SVN: r55528
parent d955f6ea
Wed Jul 17 14:04:10 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh-protos.h (binary_float_operator): Remove declaration.
(sh_expand_unop_v2sf, sh_expand_binop_v2sf): Declare.
* sh.c (print_operand, case 'N'): Check against CONST0_RTX.
(unary_float_operator, sh_expand_unop_v2sf): New functions.
(sh_expand_binop_v2sf): Likewise.
(zero_vec_operand): Delete.
(SH_BLTIN_UDI): New builtin shared signature define. Renumbered
all non-shared ones.
(bdesc): Change all the mextr builtins to use SH_BLTIN_UDI.
Enable nsb and byterev.
* sh.h (CONDITIONAL_REGISTER_USAGE): Initialize DF_HI_REGS.
(HARD_REGNO_MODE_OK): Allow TImode in fp regs. Allow V2SFmode
in general regs.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add DF_HI_REGS.
(SECONDARY_OUTPUT_RELOAD_CLASS): Likewise. Remove clause for
immediate operands.
(SECONDARY_INPUT_RELOAD_CLASS): Add clause for immediate operands.
Add DF_HI_REGS.
(CLASS_CANNOT_CHANGE_MODE, CLASS_CANNOT_CHANGE_MODE_P): Allow
lowpart fp regs - only for big endian for now.
(LEGITIMATE_CONSTANT_P): Don't allow non-zero float vectors
when FPU is in use.
(EXTRA_CONTRAINT_U): Check against CONST0_RTX.
(LOAD_EXTEND_OP): NIL for SImode.
(REGISTER_MOVE_COST): Add DF_HI_REGS. Const for moves between
general and fp registers is 4.
PREDICATE_CODES: Amend binary_float_operator entry.
Remove zero_vec_operand. Add unary_float_operator.
* sh.md (udivsi3_i4_media): Use truncate instead of paradoxical
subreg SET_DEST.
(truncdisi2, truncdihi2, movv2sf): Allow memory destinations.
(truncdiqi2): Do sign extension.
(movsi_media, movdi_media): Allow to use r63 to an fp register.
(movdf_media, movsf_media): Likewise.
(movv2sf_i, movv2sf_i+1): Don't use f{ld,st}.p or SUBREGS.
Collapse to one define_insn_and_split. Allow immediate sources.
(addv2sf3, subv2sf3, mulv2sf3, divv2sf3): New patterns.
(movv4sf_i): Allow immediate sources. Use simplify_gen_subreg.
(movv4sf): Allow immediate sources.
(movsf_media_nofpu+1): Don't split moves to FP registers.
(unary_sf_op, binary_sf_op, mshflo_w_x, concat_v2sf): New patterns.
(movv8qi_i+3): Check against CONST0_RTX.
(mextr1, mextr2. mextr3. mextr4, mextr5, mextr6, mextr7): Use DImode
for input and output operands. Fix argument 3 to gen_mextr_rl.
(mmul23_wl, mmul01_wl, mmulsum_wq_i): s/const_vector/parallel/
(msad_ubq_i, mshf4_b, mshf0_b, mshf4_l, mshf0_l, mshf4_w): Likewise.
(mshf0_w, fipr, ftrv): Likewise.
(mshfhi_l_di): Now insn_and_split. Can handle FP regs.
2002-07-17 Jeroen Dobbelaere <jeroen.dobbelaere@acunia.com> 2002-07-17 Jeroen Dobbelaere <jeroen.dobbelaere@acunia.com>
* arm.h (ARM_NUM_INTS, ARM_NUM_REGS, ARM_NUM_REGS2): Renamed from * arm.h (ARM_NUM_INTS, ARM_NUM_REGS, ARM_NUM_REGS2): Renamed from
......
...@@ -92,7 +92,6 @@ extern int fpscr_operand PARAMS ((rtx, enum machine_mode)); ...@@ -92,7 +92,6 @@ extern int fpscr_operand PARAMS ((rtx, enum machine_mode));
extern int fpul_operand PARAMS ((rtx, enum machine_mode)); extern int fpul_operand PARAMS ((rtx, enum machine_mode));
extern int commutative_float_operator PARAMS ((rtx, enum machine_mode)); extern int commutative_float_operator PARAMS ((rtx, enum machine_mode));
extern int noncommutative_float_operator PARAMS ((rtx, enum machine_mode)); extern int noncommutative_float_operator PARAMS ((rtx, enum machine_mode));
extern int binary_float_operator PARAMS ((rtx, enum machine_mode));
extern int reg_unused_after PARAMS ((rtx, rtx)); extern int reg_unused_after PARAMS ((rtx, rtx));
extern void expand_sf_unop PARAMS ((rtx (*)(rtx, rtx, rtx), rtx *)); extern void expand_sf_unop PARAMS ((rtx (*)(rtx, rtx, rtx), rtx *));
extern void expand_sf_binop PARAMS ((rtx (*)(rtx, rtx, rtx, rtx), rtx *)); extern void expand_sf_binop PARAMS ((rtx (*)(rtx, rtx, rtx, rtx), rtx *));
...@@ -118,6 +117,8 @@ extern void output_file_start PARAMS ((FILE *)); ...@@ -118,6 +117,8 @@ extern void output_file_start PARAMS ((FILE *));
extern int sh_media_register_for_return PARAMS ((void)); extern int sh_media_register_for_return PARAMS ((void));
extern void sh_expand_prologue PARAMS ((void)); extern void sh_expand_prologue PARAMS ((void));
extern void sh_expand_epilogue PARAMS ((void)); extern void sh_expand_epilogue PARAMS ((void));
extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
extern int sh_need_epilogue PARAMS ((void)); extern int sh_need_epilogue PARAMS ((void));
extern int initial_elimination_offset PARAMS ((int, int)); extern int initial_elimination_offset PARAMS ((int, int));
extern int fldi_ok PARAMS ((void)); extern int fldi_ok PARAMS ((void));
......
...@@ -449,8 +449,7 @@ print_operand (stream, x, code) ...@@ -449,8 +449,7 @@ print_operand (stream, x, code)
break; break;
case 'N': case 'N':
if (x == const0_rtx if (x == CONST0_RTX (GET_MODE (x)))
|| (GET_CODE (x) == CONST_VECTOR && zero_vec_operand (x, VOIDmode)))
{ {
fprintf ((stream), "r63"); fprintf ((stream), "r63");
break; break;
...@@ -6122,6 +6121,25 @@ noncommutative_float_operator (op, mode) ...@@ -6122,6 +6121,25 @@ noncommutative_float_operator (op, mode)
} }
int int
unary_float_operator (op, mode)
rtx op;
enum machine_mode mode;
{
if (GET_MODE (op) != mode)
return 0;
switch (GET_CODE (op))
{
case ABS:
case NEG:
case SQRT:
return 1;
default:
break;
}
return 0;
}
int
binary_float_operator (op, mode) binary_float_operator (op, mode)
rtx op; rtx op;
enum machine_mode mode; enum machine_mode mode;
...@@ -6285,23 +6303,6 @@ inqhi_operand (op, mode) ...@@ -6285,23 +6303,6 @@ inqhi_operand (op, mode)
return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op)); return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
} }
/* Return nonzero if V is a zero vector matching MODE. */
int
zero_vec_operand (v, mode)
rtx v;
enum machine_mode mode;
{
int i;
if (GET_CODE (v) != CONST_VECTOR
|| (GET_MODE (v) != mode && mode != VOIDmode))
return 0;
for (i = XVECLEN (v, 0) - 1; i >= 0; i--)
if (XVECEXP (v, 0, i) != const0_rtx)
return 0;
return 1;
}
int int
sh_rep_vec (v, mode) sh_rep_vec (v, mode)
rtx v; rtx v;
...@@ -7156,19 +7157,21 @@ static const char signature_args[][4] = ...@@ -7156,19 +7157,21 @@ static const char signature_args[][4] =
{ 0, 8, 2 }, { 0, 8, 2 },
#define SH_BLTIN_STUA_Q 14 #define SH_BLTIN_STUA_Q 14
{ 0, 8, 1 }, { 0, 8, 1 },
#define SH_BLTIN_NUM_SHARED_SIGNATURES 15 #define SH_BLTIN_UDI 15
#define SH_BLTIN_2 15 { 0, 8, 1 },
#define SH_BLTIN_SU 15 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
#define SH_BLTIN_2 16
#define SH_BLTIN_SU 16
{ 1, 2 }, { 1, 2 },
#define SH_BLTIN_3 16 #define SH_BLTIN_3 17
#define SH_BLTIN_SUS 16 #define SH_BLTIN_SUS 17
{ 2, 2, 1 }, { 2, 2, 1 },
#define SH_BLTIN_PSSV 17 #define SH_BLTIN_PSSV 18
{ 0, 8, 2, 2 }, { 0, 8, 2, 2 },
#define SH_BLTIN_XXUU 18 #define SH_BLTIN_XXUU 19
#define SH_BLTIN_UUUU 18 #define SH_BLTIN_UUUU 19
{ 1, 1, 1, 1 }, { 1, 1, 1, 1 },
#define SH_BLTIN_PV 19 #define SH_BLTIN_PV 20
{ 0, 8 }, { 0, 8 },
}; };
/* mcmv: operands considered unsigned. */ /* mcmv: operands considered unsigned. */
...@@ -7200,13 +7203,13 @@ static const struct builtin_description bdesc[] = ...@@ -7200,13 +7203,13 @@ static const struct builtin_description bdesc[] =
{ CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 }, { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
{ CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI }, { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
{ CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI }, { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
{ CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
{ CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
{ CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
{ CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
{ CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
{ CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
{ CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 }, { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
{ CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI }, { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
{ CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI }, { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
{ CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, }, { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
...@@ -7261,8 +7264,10 @@ static const struct builtin_description bdesc[] = ...@@ -7261,8 +7264,10 @@ static const struct builtin_description bdesc[] =
{ CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q }, { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
{ CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L }, { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
{ CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q }, { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
#endif
{ CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU }, { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
{ CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 }, { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
#if 0
{ CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }, { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
{ CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV } { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
#endif #endif
...@@ -7408,4 +7413,33 @@ sh_expand_builtin (exp, target, subtarget, mode, ignore) ...@@ -7408,4 +7413,33 @@ sh_expand_builtin (exp, target, subtarget, mode, ignore)
emit_insn (pat); emit_insn (pat);
return target; return target;
} }
void
sh_expand_unop_v2sf (code, op0, op1)
enum rtx_code code;
rtx op0, op1;
{
rtx sel0 = const0_rtx;
rtx sel1 = const1_rtx;
rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
rtx op = gen_rtx_fmt_e (code, SFmode, op1);
emit_insn ((*fn) (op0, op1, op, sel0, sel0));
emit_insn ((*fn) (op0, op1, op, sel1, sel1));
}
void
sh_expand_binop_v2sf (code, op0, op1, op2)
enum rtx_code code;
rtx op0, op1, op2;
{
rtx sel0 = const0_rtx;
rtx sel1 = const1_rtx;
rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx) = gen_binary_sf_op;
rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0));
emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1));
}
#include "gt-sh.h" #include "gt-sh.h"
...@@ -106,6 +106,9 @@ do { \ ...@@ -106,6 +106,9 @@ do { \
call_used_regs[MACH_REG] = 0; \ call_used_regs[MACH_REG] = 0; \
call_used_regs[MACL_REG] = 0; \ call_used_regs[MACL_REG] = 0; \
} \ } \
for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
regno <= LAST_FP_REG; regno += 2) \
SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
if (TARGET_SHMEDIA) \ if (TARGET_SHMEDIA) \
{ \ { \
for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\ for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
...@@ -893,13 +896,16 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -893,13 +896,16 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
would require a tertiary reload when reloading from / to memory, would require a tertiary reload when reloading from / to memory,
and a secondary reload to reload from / to general regs; that and a secondary reload to reload from / to general regs; that
seems to be a loosing proposition. */ seems to be a loosing proposition. */
/* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
it won't be ferried through GP registers first. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \ #define HARD_REGNO_MODE_OK(REGNO, MODE) \
(SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \ (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
: (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
: FP_REGISTER_P (REGNO) && (MODE) == SFmode \ : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
? 1 \ ? 1 \
: (MODE) == V2SFmode \ : (MODE) == V2SFmode \
? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \ ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
|| (TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
: (MODE) == V4SFmode \ : (MODE) == V4SFmode \
? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \ ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
: (MODE) == V16SFmode \ : (MODE) == V16SFmode \
...@@ -912,7 +918,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ ...@@ -912,7 +918,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
|| ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \ || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|| (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \ || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
|| (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \ || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
|| (MODE) == V2SFmode))) \ || (MODE) == V2SFmode || (MODE) == TImode))) \
&& (((REGNO) - FIRST_FP_REG) & 1) == 0)) \ && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
: XD_REGISTER_P (REGNO) \ : XD_REGISTER_P (REGNO) \
? (MODE) == DFmode \ ? (MODE) == DFmode \
...@@ -1106,6 +1112,7 @@ enum reg_class ...@@ -1106,6 +1112,7 @@ enum reg_class
GENERAL_REGS, GENERAL_REGS,
FP0_REGS, FP0_REGS,
FP_REGS, FP_REGS,
DF_HI_REGS,
DF_REGS, DF_REGS,
FPSCR_REGS, FPSCR_REGS,
GENERAL_FP_REGS, GENERAL_FP_REGS,
...@@ -1129,6 +1136,7 @@ enum reg_class ...@@ -1129,6 +1136,7 @@ enum reg_class
"GENERAL_REGS", \ "GENERAL_REGS", \
"FP0_REGS", \ "FP0_REGS", \
"FP_REGS", \ "FP_REGS", \
"DF_HI_REGS", \
"DF_REGS", \ "DF_REGS", \
"FPSCR_REGS", \ "FPSCR_REGS", \
"GENERAL_FP_REGS", \ "GENERAL_FP_REGS", \
...@@ -1162,6 +1170,8 @@ enum reg_class ...@@ -1162,6 +1170,8 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
/* FP_REGS: */ \ /* FP_REGS: */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
/* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
/* DF_REGS: */ \ /* DF_REGS: */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
/* FPSCR_REGS: */ \ /* FPSCR_REGS: */ \
...@@ -1286,7 +1296,7 @@ extern const enum reg_class reg_class_from_letter[]; ...@@ -1286,7 +1296,7 @@ extern const enum reg_class reg_class_from_letter[];
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \ ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
|| (CLASS) == DF_REGS) \ || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) \
&& (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \ && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
|| (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \ || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
&& GET_CODE (X) == REG \ && GET_CODE (X) == REG \
...@@ -1301,9 +1311,6 @@ extern const enum reg_class reg_class_from_letter[]; ...@@ -1301,9 +1311,6 @@ extern const enum reg_class reg_class_from_letter[];
|| REGNO (X) == T_REG \ || REGNO (X) == T_REG \
|| system_reg_operand (X, VOIDmode))))) \ || system_reg_operand (X, VOIDmode))))) \
? GENERAL_REGS \ ? GENERAL_REGS \
: (((CLASS) == FP_REGS || (CLASS) == DF_REGS) && TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE))) \
? GENERAL_REGS \
: ((CLASS) == TARGET_REGS \ : ((CLASS) == TARGET_REGS \
|| (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \ || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
? ((target_operand ((X), (MODE)) \ ? ((target_operand ((X), (MODE)) \
...@@ -1312,10 +1319,14 @@ extern const enum reg_class reg_class_from_letter[]; ...@@ -1312,10 +1319,14 @@ extern const enum reg_class reg_class_from_letter[];
: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
&& GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \ && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
? GENERAL_REGS \
: ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
&& TARGET_REGISTER_P (REGNO (X))) \
? GENERAL_REGS : NO_REGS) ? GENERAL_REGS : NO_REGS)
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \ ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS \
|| (CLASS) == DF_HI_REGS) \
&& ! TARGET_SHMEDIA \ && ! TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE)) \ && immediate_operand ((X), (MODE)) \
&& ! ((fp_zero_operand (X) || fp_one_operand (X)) \ && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
...@@ -1334,6 +1345,12 @@ extern const enum reg_class reg_class_from_letter[]; ...@@ -1334,6 +1345,12 @@ extern const enum reg_class reg_class_from_letter[];
&& ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\ || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
? GENERAL_REGS \ ? GENERAL_REGS \
: (((CLASS) == FP_REGS || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)\
&& TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE)) \
&& (X) != CONST0_RTX (GET_MODE (X)) \
&& GET_MODE (X) != V4SFmode) \
? GENERAL_REGS \
: SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X))) : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
/* Return the maximum number of consecutive registers /* Return the maximum number of consecutive registers
...@@ -1345,13 +1362,17 @@ extern const enum reg_class reg_class_from_letter[]; ...@@ -1345,13 +1362,17 @@ extern const enum reg_class reg_class_from_letter[];
/* If defined, gives a class of registers that cannot be used as the /* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */ operand of a SUBREG that changes the mode of the object illegally. */
/* ??? We need to renumber the internal numbers for the frnn registers
when in little endian in order to allow mode size changes. */
#define CLASS_CANNOT_CHANGE_MODE DF_REGS #define CLASS_CANNOT_CHANGE_MODE (TARGET_LITTLE_ENDIAN ? DF_REGS : DF_HI_REGS)
/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
&& ((TARGET_LITTLE_ENDIAN && GET_MODE_SIZE (TO) < 8) \
|| GET_MODE_SIZE (FROM) < 8))
/* Stack layout; function entry, exit and calling. */ /* Stack layout; function entry, exit and calling. */
...@@ -2192,7 +2213,8 @@ while (0) ...@@ -2192,7 +2213,8 @@ while (0)
#define LEGITIMATE_CONSTANT_P(X) \ #define LEGITIMATE_CONSTANT_P(X) \
(TARGET_SHMEDIA \ (TARGET_SHMEDIA \
? (GET_MODE (X) != DFmode \ ? ((GET_MODE (X) != DFmode \
&& GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
|| (X) == CONST0_RTX (GET_MODE (X)) \ || (X) == CONST0_RTX (GET_MODE (X)) \
|| ! TARGET_SHMEDIA_FPU \ || ! TARGET_SHMEDIA_FPU \
|| TARGET_SHMEDIA64) \ || TARGET_SHMEDIA64) \
...@@ -2316,10 +2338,7 @@ while (0) ...@@ -2316,10 +2338,7 @@ while (0)
/* A zero in any shape or form. */ /* A zero in any shape or form. */
#define EXTRA_CONSTRAINT_U(OP) \ #define EXTRA_CONSTRAINT_U(OP) \
((OP) == const0_rtx \ ((OP) == CONST0_RTX (GET_MODE (OP)))
|| (GET_CODE (OP) == SUBREG && VECTOR_MODE_SUPPORTED_P(GET_MODE (OP)) \
&& SUBREG_REG (OP) == const0_rtx && SUBREG_BYTE (OP) == 0) \
|| GET_CODE (OP) == CONST_VECTOR && zero_vec_operand ((OP), VOIDmode))
/* Any vector constant we can handle. */ /* Any vector constant we can handle. */
#define EXTRA_CONSTRAINT_W(OP) \ #define EXTRA_CONSTRAINT_W(OP) \
...@@ -2642,7 +2661,9 @@ while (0) ...@@ -2642,7 +2661,9 @@ while (0)
will either zero-extend or sign-extend. The value of this macro should will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly be the code that says which one of the two operations is implicitly
done, NIL if none. */ done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND /* FP registers can load SImode values, but don't implicitly sign-extend
them to DImode. */
#define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : NIL)
/* Define if loading short immediate values into registers sign extends. */ /* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND #define SHORT_IMMEDIATES_SIGN_EXTEND
...@@ -2821,12 +2842,13 @@ while (0) ...@@ -2821,12 +2842,13 @@ while (0)
register information here is not used for SFmode. */ register information here is not used for SFmode. */
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \ #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
(((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \ (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
: ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \ : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
|| (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
&& ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \ && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
|| (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \ || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
&& ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \ && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
|| (SRCCLASS) == DF_REGS))) \ || (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
? (TARGET_SHMEDIA ? 2 \ ? (TARGET_SHMEDIA ? 4 \
: TARGET_FMOVD ? 8 : 12) \ : TARGET_FMOVD ? 8 : 12) \
: (((DSTCLASS) == FPUL_REGS \ : (((DSTCLASS) == FPUL_REGS \
&& ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \ && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
...@@ -3231,7 +3253,7 @@ extern int rtx_equal_function_value_matters; ...@@ -3231,7 +3253,7 @@ extern int rtx_equal_function_value_matters;
{"arith_reg_dest", {SUBREG, REG}}, \ {"arith_reg_dest", {SUBREG, REG}}, \
{"arith_reg_operand", {SUBREG, REG}}, \ {"arith_reg_operand", {SUBREG, REG}}, \
{"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \ {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
{"binary_float_operator", {PLUS, MULT}}, \ {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
{"commutative_float_operator", {PLUS, MULT}}, \ {"commutative_float_operator", {PLUS, MULT}}, \
{"equality_comparison_operator", {EQ,NE}}, \ {"equality_comparison_operator", {EQ,NE}}, \
{"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \ {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
...@@ -3256,7 +3278,7 @@ extern int rtx_equal_function_value_matters; ...@@ -3256,7 +3278,7 @@ extern int rtx_equal_function_value_matters;
{"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \ {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
{"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \ {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
{"symbol_ref_operand", {SYMBOL_REF}}, \ {"symbol_ref_operand", {SYMBOL_REF}}, \
{"zero_vec_operand", {CONST_VECTOR}}, {"unary_float_operator", {ABS, NEG, SQRT}}, \
/* Define this macro if it is advisable to hold scalars in registers /* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases, in a wider mode than that declared by the program. In such cases,
......
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