sh.h (TARGET_HARWARD, [...]): Changed the former to the latter.

	* sh.h (TARGET_HARWARD, TARGET_HARVARD): Changed the former to the
	latter.
	* sh.md (ic_invalidate_line_i): Remove second alternative.

From-SVN: r27469

gcc/ChangeLog

+Thu Jun 10 19:23:00 1999  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh.h (TARGET_HARWARD, TARGET_HARVARD): Changed the former to the
+	latter.
+
+	* sh.md (ic_invalidate_line_i): Remove second alternative.
+
 Thu Jun 10 06:55 1999  Bruce Korb <ddsinc09@ix.netcom.com>
 
 	*fixinc/inclhack.def(sun_auth_proto): We do not know how to

gcc/config/sh/sh.h

@@ -131,7 +131,7 @@ extern int target_flags;
 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
 
 /* Nonzero if the target has separate instruction and data caches.  */
-#define TARGET_HARWARD (target_flags & HARD_SH4_BIT)
+#define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
 
 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.)  */
 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
@@ -354,7 +354,7 @@ do {									\
   barrier_align (LABEL_AFTER_BARRIER)
 
 #define LOOP_ALIGN(A_LABEL) \
-  ((! optimize || TARGET_HARWARD || TARGET_SMALLCODE) ? 0 : 2)
+  ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) ? 0 : 2)
 
 #define LABEL_ALIGN(A_LABEL) \
 (									\
@@ -1123,7 +1123,7 @@ extern int current_function_anonymous_args;
 
 /* Alignment required for a trampoline in bits .  */
 #define TRAMPOLINE_ALIGNMENT \
-  ((CACHE_LOG < 3 || TARGET_SMALLCODE && ! TARGET_HARWARD) ? 32 : 64)
+  ((CACHE_LOG < 3 || TARGET_SMALLCODE && ! TARGET_HARVARD) ? 32 : 64)
 
 /* Emit RTL insns to initialize the variable parts of a trampoline.
    FNADDR is an RTX for the address of the function's pure code.
@@ -1139,7 +1139,7 @@ extern int current_function_anonymous_args;
 		  (CXT));						\
   emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)),	\
 		  (FNADDR));						\
-  if (TARGET_HARWARD)							\
+  if (TARGET_HARVARD)							\
     emit_insn (gen_ic_invalidate_line (TRAMP));				\
 }
 

gcc/config/sh/sh.md

@@ -2242,16 +2242,16 @@
 }")
 
 ;; The address %0 is assumed to be 4-aligned at least.  Thus, by ORing
-;; 0xf0000008, we get the low-oder bits *1*00 (binary), ;; which fits
-;; the requirement *0*00 for associative address writes.  The alignment of
+;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
+;; the requirement *1*00 for associative address writes.  The alignment of
 ;; %0 implies that its least significant bit is cleared,
 ;; thus we clear the V bit of a matching entry if there is one.
 (define_insn "ic_invalidate_line_i"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r,r")
-		     (match_operand:SI 1 "register_operand" "r,r")] 12)
-   (clobber (match_scratch:SI 2 "=&r,1"))]
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
+		     (match_operand:SI 1 "register_operand" "r")] 12)
+   (clobber (match_scratch:SI 2 "=&r"))]
   "TARGET_HARD_SH4"
-  "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%r1,%r2\;mov.l\\t%0,@%2"
+  "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
   [(set_attr "length" "8")])
 
 (define_insn "movqi_i"