i386.h (TARGET_ABM): New define.

	* config/i386/i386.h (TARGET_ABM): New define.
	(TARGET_POPCNT): Ditto.
	(TARGET_64BIT, TARGET_MMX, TARGET_3DNOW, TARGET_3DNOW_A, TARGET_SSE*):
	New temporary defines to redefine from OPTION_ISA_* defines.
	(MASK_64BIT, MASK_MMX, MASK_3DNOW, MASK_3DNOW_A, MASK_SSE*):
	New temporary defines to redefine from OPTION_MASK_ISA_* defines.
	(ix86_isa_flags): New extern int declaration.
	(TARGET_SUBTARGET_DEFAULT): New define.
	(TARGET_SUBTARGET_ISA_DEFAULT): Ditto.
	(TARGET_SUBTARGET32_DEFAULT): Ditto.
	(TARGET_SUBTARGET32_ISA_DEFAULT): Ditto.
	(TARGET_SUBTARGET64_ISA_DEFAULT): Ditto.
	* config/i386/unix.h: Undef TARGET_SUBTARGET_DEFAULT before define.
	* config/i386/darwin.h: Change TARGET_64BIT define to
	OPTION_ISA_64BIT.

	* config/i386/i386.opt (m3dnowa): Define as undocumented option
	using existing "ix86_isa_flags" varible.
	(m32, m64): Use existing "ix86_isa_flags" variable.
	(mmmx, m3dnow): Ditto.
	(msse, msse2, msse3, mssse3, msse4.1, msse4a): Ditto.
	(mabm): Define as non-negative option using "x86_abm" variable.
	(mpopcnt): Define as non-negative option using "x86_popcnt" variable.

	* config/i386/i386.c (ix86_arch_features) [X86_ARCH_CMOVE]:
	Rewrite feature test bitmap.
	(ix86_isa_flags): New initialized global int varible.
	(ix86_isa_flags_explicit): New static int variable.
	(ix86_handle_option): Set "ix86_isa_flags_explicit" when mmmx, m3dnow,
	msse, msse2, msse3, msse4.1 and msse4a option is processed.  Change
	i86_isa_flags and ix86_isa_flags_explicit, not target_flags and
	target_flags_explicit.
	(override_options): Remove "target_enable" and "target_disable" fields
	from "struct ptt". Update processor_target_table accordingly. Remove
	PTA_PREFETCH_SSE from processor_alias_table entry if PTE_SSE is
	defined and rearrange PTA_* bits.  Use "ix86_isa_flags" instead of
	"target_flags" and "ix86_isa_flags_explicit" instead of
	"target_flags_explicit" when masked with MASK_64BIT, MASK_MMX,
	MASK_3DNOW, MASK_3DNOW_A or MASK_SSE*.  Set "x86_abm" to true when
	PTA_ABM is set in processor_alias_table flags entry.  Set "x86_popcnt"
	to true when either of PTA_POPCNT or PTA_ABM is set in
	processor_alias_table flags entry.  Set "x86_prefetch_sse" to true
	when either of PTA_PREFETCH_SSE or PTA_SSE is set in
	processor_alias_table flags entry.  Remove handling of
	"target_enable" and "target_disable" fields of processor_target_table.
	Mask "target_flags" with TARGET_SUBTARGET32_DEFAULT for 32-bit
	targets or with TARGET_SUBTARGET64_DEFAULT for 64-bit targets.
	Mask "ix86_isa_flags" with TARGET_SUBTARGET32_ISA_DEFAULT for 32-bit
	targets or with TARGET_SUBTARGET64_ISA_DEFAULT for 64-bit targets.
	(def_builtin): Mask "mask" variable with "ix86_isa_flags", not
	"target_flags".
	(TARGET_DEFAULT_TARGET_FLAGS): Do not include TARGET_64BIT_DEFAULT.

From-SVN: r125180

gcc/ChangeLog

+2007-05-30 Uros Bizjak <ubizjak@gmail.com>
+
+	* config/i386/i386.h (TARGET_ABM): New define.
+	(TARGET_POPCNT): Ditto.
+	(TARGET_64BIT, TARGET_MMX, TARGET_3DNOW, TARGET_3DNOW_A, TARGET_SSE*):
+	New temporary defines to redefine from OPTION_ISA_* defines.
+	(MASK_64BIT, MASK_MMX, MASK_3DNOW, MASK_3DNOW_A, MASK_SSE*):
+	New temporary defines to redefine from OPTION_MASK_ISA_* defines.
+	(ix86_isa_flags): New extern int declaration.
+	(TARGET_SUBTARGET_DEFAULT): New define.
+	(TARGET_SUBTARGET_ISA_DEFAULT): Ditto.
+	(TARGET_SUBTARGET32_DEFAULT): Ditto.
+	(TARGET_SUBTARGET32_ISA_DEFAULT): Ditto.
+	(TARGET_SUBTARGET64_ISA_DEFAULT): Ditto.
+	* config/i386/unix.h: Undef TARGET_SUBTARGET_DEFAULT before define.
+	* config/i386/darwin.h: Change TARGET_64BIT define to
+	OPTION_ISA_64BIT.
+
+	* config/i386/i386.opt (m3dnowa): Define as undocumented option
+	using existing "ix86_isa_flags" varible.
+	(m32, m64): Use existing "ix86_isa_flags" variable.
+	(mmmx, m3dnow): Ditto.
+	(msse, msse2, msse3, mssse3, msse4.1, msse4a): Ditto.
+	(mabm): Define as non-negative option using "x86_abm" variable.
+	(mpopcnt): Define as non-negative option using "x86_popcnt" variable.
+
+	* config/i386/i386.c (ix86_arch_features) [X86_ARCH_CMOVE]:
+	Rewrite feature test bitmap.
+	(ix86_isa_flags): New initialized global int varible.
+	(ix86_isa_flags_explicit): New static int variable.
+	(ix86_handle_option): Set "ix86_isa_flags_explicit" when mmmx, m3dnow,
+	msse, msse2, msse3, msse4.1 and msse4a option is processed.  Change
+	i86_isa_flags and ix86_isa_flags_explicit, not target_flags and
+	target_flags_explicit.
+	(override_options): Remove "target_enable" and "target_disable" fields
+	from "struct ptt". Update processor_target_table accordingly. Remove
+	PTA_PREFETCH_SSE from processor_alias_table entry if PTE_SSE is
+	defined and rearrange PTA_* bits.  Use "ix86_isa_flags" instead of
+	"target_flags" and "ix86_isa_flags_explicit" instead of
+	"target_flags_explicit" when masked with MASK_64BIT, MASK_MMX,
+	MASK_3DNOW, MASK_3DNOW_A or MASK_SSE*.  Set "x86_abm" to true when
+	PTA_ABM is set in processor_alias_table flags entry.  Set "x86_popcnt"
+	to true when either of PTA_POPCNT or PTA_ABM is set in
+	processor_alias_table flags entry.  Set "x86_prefetch_sse" to true
+	when either of PTA_PREFETCH_SSE or PTA_SSE is set in
+	processor_alias_table flags entry.  Remove handling of
+	"target_enable" and "target_disable" fields of processor_target_table.
+	Mask "target_flags" with TARGET_SUBTARGET32_DEFAULT for 32-bit
+	targets or with TARGET_SUBTARGET64_DEFAULT for 64-bit targets.
+	Mask "ix86_isa_flags" with TARGET_SUBTARGET32_ISA_DEFAULT for 32-bit
+	targets or with TARGET_SUBTARGET64_ISA_DEFAULT for 64-bit targets.
+	(def_builtin): Mask "mask" variable with "ix86_isa_flags", not
+	"target_flags".
+	(TARGET_DEFAULT_TARGET_FLAGS): Do not include TARGET_64BIT_DEFAULT.
+
 2007-05-29  David Daney  <ddaney@avtrex.com
 
 	PR gcc/31975
@@ -119,7 +174,6 @@
 	* varpool.c (add_new_static_var): New function.
 	* cgraph.h (add_new_static_var): Declare.
 
-
 2007-05-27  Eric Christopher  <echristo@apple.com>
 
 	* config/rs6000/rs6000.c (rs6000_emit_prologue): Update
@@ -136,7 +190,8 @@
 	* tree-ssa-threadupdate.c (thread_block): Ditto.
 	(thread_through_all_blocks): Ditto.  Assert that loops were analysed.
 	* tree-ssa-loop-manip.c (rewrite_into_loop_closed_ssa,
-	verify_loop_closed_ssa): Check number_of_loops instead of current_loops.
+	verify_loop_closed_ssa): Check number_of_loops instead of
+	current_loops.
 	* predict.c (tree_estimate_probability): Ditto.
 	* tree-if-conv.c (main_tree_if_conversion): Ditto.
 	* tree-ssa-loop-ch.c (copy_loop_headers): Ditto.

gcc/config/i386/darwin.h

@@ -26,7 +26,7 @@ Boston, MA 02110-1301, USA.  */
 #define TARGET_VERSION fprintf (stderr, " (i686 Darwin)");
 
 #undef  TARGET_64BIT
-#define TARGET_64BIT (target_flags & MASK_64BIT)
+#define TARGET_64BIT OPTION_ISA_64BIT
 
 #ifdef IN_LIBGCC2
 #undef TARGET_64BIT

gcc/config/i386/i386.h

@@ -35,6 +35,32 @@ Boston, MA 02110-1301, USA.  */
    ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
    that start with ASM_ or end in ASM_OP.  */
 
+/* Redefines for option macros.  */
+
+#define TARGET_64BIT	OPTION_ISA_64BIT
+#define TARGET_MMX	OPTION_ISA_MMX
+#define TARGET_3DNOW	OPTION_ISA_3DNOW
+#define TARGET_3DNOW_A	OPTION_ISA_3DNOW_A
+#define TARGET_SSE	OPTION_ISA_SSE
+#define TARGET_SSE2	OPTION_ISA_SSE2
+#define TARGET_SSE3	OPTION_ISA_SSE3
+#define TARGET_SSSE3	OPTION_ISA_SSSE3
+#define TARGET_SSE4_1	OPTION_ISA_SSE4_1
+#define TARGET_SSE4A	OPTION_ISA_SSE4A
+
+/* ??? Remove following defines.  */
+
+#define MASK_64BIT	OPTION_MASK_ISA_64BIT
+#define MASK_MMX	OPTION_MASK_ISA_MMX
+#define MASK_3DNOW	OPTION_MASK_ISA_3DNOW
+#define MASK_3DNOW_A	OPTION_MASK_ISA_3DNOW_A
+#define MASK_SSE	OPTION_MASK_ISA_SSE
+#define MASK_SSE2	OPTION_MASK_ISA_SSE2
+#define MASK_SSE3	OPTION_MASK_ISA_SSE3
+#define MASK_SSSE3	OPTION_MASK_ISA_SSSE3
+#define MASK_SSE4_1	OPTION_MASK_ISA_SSE4_1
+#define MASK_SSE4A	OPTION_MASK_ISA_SSE4A
+
 #include "config/vxworks-dummy.h"
 
 /* Algorithm to expand string function with.  */
@@ -342,13 +368,15 @@ extern unsigned int ix86_arch_features[X86_ARCH_LAST];
 #define TARGET_XADD		ix86_arch_features[X86_ARCH_XADD]
 #define TARGET_BSWAP		ix86_arch_features[X86_ARCH_BSWAP]
 
-#define TARGET_CMPXCHG16B	x86_cmpxchg16b
-#define TARGET_SAHF		x86_sahf
-
 #define TARGET_FISTTP		(TARGET_SSE3 && TARGET_80387)
 
 extern int x86_prefetch_sse;
+
+#define TARGET_ABM		x86_abm
+#define TARGET_CMPXCHG16B	x86_cmpxchg16b
+#define TARGET_POPCNT		x86_popcnt
 #define TARGET_PREFETCH_SSE	x86_prefetch_sse
+#define TARGET_SAHF		x86_sahf
 
 #define ASSEMBLER_DIALECT	(ix86_asm_dialect)
 
@@ -361,6 +389,8 @@ extern int x86_prefetch_sse;
 #define TARGET_ANY_GNU_TLS	(TARGET_GNU_TLS || TARGET_GNU2_TLS)
 #define TARGET_SUN_TLS		(ix86_tls_dialect == TLS_DIALECT_SUN)
 
+extern int ix86_isa_flags;
+
 #ifndef TARGET_64BIT_DEFAULT
 #define TARGET_64BIT_DEFAULT 0
 #endif
@@ -373,8 +403,17 @@ extern int x86_prefetch_sse;
    the frame pointer in leaf functions.  */
 #define TARGET_DEFAULT 0
 
+/* Extra bits to force.  */
+#define TARGET_SUBTARGET_DEFAULT 0
+#define TARGET_SUBTARGET_ISA_DEFAULT 0
+
+/* Extra bits to force on w/ 32-bit mode.  */
+#define TARGET_SUBTARGET32_DEFAULT 0
+#define TARGET_SUBTARGET32_ISA_DEFAULT 0
+
 /* Extra bits to force on w/ 64-bit mode.  */
 #define TARGET_SUBTARGET64_DEFAULT 0
+#define TARGET_SUBTARGET64_ISA_DEFAULT 0
 
 /* This is not really a target flag, but is done this way so that
    it's analogous to similar code for Mach-O on PowerPC.  darwin.h

gcc/config/i386/i386.opt

@@ -23,18 +23,6 @@ m128bit-long-double
 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE)
 sizeof(long double) is 16
 
-m32
-Target RejectNegative Negative(m64) Report InverseMask(64BIT)
-Generate 32bit i386 code
-
-m3dnow
-Target Report Mask(3DNOW)
-Support 3DNow! built-in functions
-
-m64
-Target RejectNegative Negative(m32) Report Mask(64BIT)
-Generate 64bit x86-64 code
-
 m80387
 Target Report Mask(80387)
 Use hardware fp
@@ -119,10 +107,6 @@ mintel-syntax
 Target Undocumented
 ;; Deprecated
 
-mmmx
-Target Report Mask(MMX)
-Support MMX built-in functions
-
 mms-bitfields
 Target Report Mask(MS_BITFIELD_LAYOUT)
 Use native (MS) bitfield layout
@@ -171,50 +155,6 @@ msoft-float
 Target InverseMask(80387)
 Do not use hardware fp
 
-msse
-Target Report Mask(SSE)
-Support MMX and SSE built-in functions and code generation
-
-msse2
-Target Report Mask(SSE2)
-Support MMX, SSE and SSE2 built-in functions and code generation
-
-msse3
-Target Report Mask(SSE3)
-Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
-
-mssse3
-Target Report Mask(SSSE3)
-Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
-
-msse4.1
-Target Report Mask(SSE4_1)
-Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
-
-msse4a
-Target Report Mask(SSE4A)
-Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
-
-mpopcnt
-Target Report Mask(POPCNT)
-Support code generation of popcnt instruction for popcount built-ins 
-namely __builtin_popcount, __builtin_popcountl and __builtin_popcountll
-
-mabm
-Target Report Mask(ABM)
-Support code generation of Advanced Bit Manipulation (ABM) instructions,
-which include popcnt and lzcnt instructions, for popcount and clz built-ins
-namely __builtin_popcount, __builtin_popcountl, __builtin_popcountll and
-__builtin_clz, __builtin_clzl, __builtin_clzll
-
-mcx16
-Target Report RejectNegative Var(x86_cmpxchg16b)
-Support code generation of cmpxchg16b instruction.
-
-msahf
-Target Report RejectNegative Var(x86_sahf)
-Support code generation of sahf instruction in 64bit x86-64 code
-
 msseregparm
 Target RejectNegative Mask(SSEREGPARM)
 Use SSE register passing conventions for SF and DF mode
@@ -243,5 +183,66 @@ mtune=
 Target RejectNegative Joined Var(ix86_tune_string)
 Schedule code for given CPU
 
-;; Support Athlon 3Dnow builtins
-Mask(3DNOW_A)
+;; ISA support
+
+m32
+Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists
+Generate 32bit i386 code
+
+m64
+Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists
+Generate 64bit x86-64 code
+
+mmmx
+Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists
+Support MMX built-in functions
+
+m3dnow
+Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists
+Support 3DNow! built-in functions
+
+m3dnowa
+Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists
+Support Athlon 3Dnow! built-in functions
+
+msse
+Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists
+Support MMX and SSE built-in functions and code generation
+
+msse2
+Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists
+Support MMX, SSE and SSE2 built-in functions and code generation
+
+msse3
+Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists
+Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
+
+mssse3
+Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists
+Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
+
+msse4.1
+Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists
+Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
+
+msse4a
+Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists
+Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
+
+;; Instruction support
+
+mabm
+Target Report RejectNegative Var(x86_abm)
+Support code generation of Advanced Bit Manipulation (ABM) instructions.
+
+mcx16
+Target Report RejectNegative Var(x86_cmpxchg16b)
+Support code generation of cmpxchg16b instruction.
+
+mpopcnt
+Target Report RejectNegative Var(x86_popcnt)
+Support code generation of popcnt instruction.
+
+msahf
+Target Report RejectNegative Var(x86_sahf)
+Support code generation of sahf instruction in 64bit x86-64 code.

gcc/config/i386/unix.h

@@ -61,6 +61,7 @@ Boston, MA 02110-1301, USA.  */
 
 /* By default, target has a 80387, uses IEEE compatible arithmetic,
    and returns float values in the 387.  */
+#undef TARGET_SUBTARGET_DEFAULT
 #define TARGET_SUBTARGET_DEFAULT \
 	(MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS)