constraints.md (Wcv): Allow up to $r31.

* config/rl78/constraints.md (Wcv): Allow up to $r31.
* config/rl78/rl78.c (rl78_asm_file_start: Likewise.
(rl78_option_override): Likewise, if -mallregs.
(is_virtual_register): Likewise.
* config/rl78/rl78.h (reg_class): Extend VREGS to $r31.
(REGNO_OK_FOR_BASE_P): Likewise.
* config/rl78/rl78.opt (-mallregs): New.

From-SVN: r202669

gcc/ChangeLog

+2013-09-17  DJ Delorie  <dj@redhat.com>
+
+	* config/rl78/constraints.md (Wcv): Allow up to $r31.
+	* config/rl78/rl78.c (rl78_asm_file_start: Likewise.
+	(rl78_option_override): Likewise, if -mallregs.
+	(is_virtual_register): Likewise.
+	* config/rl78/rl78.h (reg_class): Extend VREGS to $r31.
+	(REGNO_OK_FOR_BASE_P): Likewise.
+	* config/rl78/rl78.opt (-mallregs): New.
+
 2013-09-17  Nick Clifton  <nickc@redhat.com>
 
 	* config/rl78/rl78.c (need_to_save): Change return type to bool.

gcc/config/rl78/constraints.md

@@ -263,10 +263,10 @@
   )
 
 (define_memory_constraint "Ccv"
-  "[AX..HL,r8-r23] for calls"
+  "[AX..HL,r8-r31] for calls"
   (and (match_code "mem")
        (and (match_code "reg" "0")
-	    (match_test "REGNO (XEXP (op, 0)) < 24")))
+	    (match_test "REGNO (XEXP (op, 0)) < 31")))
   )
 (define_memory_constraint "Wcv"
   "es:[AX..HL,r8-r23] for calls"

gcc/config/rl78/rl78.c

@@ -272,6 +272,7 @@ rl78_asm_file_start (void)
 	{
 	  fprintf (asm_out_file, "r%d\t=\t0x%x\n", 8 + i, 0xffef0 + i);
 	  fprintf (asm_out_file, "r%d\t=\t0x%x\n", 16 + i, 0xffee8 + i);
+	  fprintf (asm_out_file, "r%d\t=\t0x%x\n", 24 + i, 0xffee0 + i);
 	}
     }
 
@@ -309,6 +310,13 @@ rl78_option_override (void)
   flag_split_wide_types = 0;
 
   init_machine_status = rl78_init_machine_status;
+
+  if (TARGET_ALLREGS)
+    {
+      int i;
+      for (i=24; i<32; i++)
+	fixed_regs[i] = 0;
+    }
 }
 
 /* Most registers are 8 bits.  Some are 16 bits because, for example,
@@ -2215,7 +2223,7 @@ is_virtual_register (rtx r)
 {
   return (GET_CODE (r) == REG
 	  && REGNO (r) >= 8
-	  && REGNO (r) < 24);
+	  && REGNO (r) < 32);
 }
 
 /* In all these alloc routines, we expect the following: the insn

gcc/config/rl78/rl78.h

@@ -265,7 +265,7 @@ enum reg_class
   { 0x00000300, 0x00000000 }, 	/* R8 - HImode */		\
   { 0x00000c00, 0x00000000 }, 	/* R10 - HImode */		\
   { 0xff000000, 0x00000000 }, 	/* INT - HImode */		\
-  { 0x007fff00, 0x00000000 },	/* Virtual registers.  */	\
+  { 0xff7fff00, 0x00000000 },	/* Virtual registers.  */	\
   { 0xff7fffff, 0x00000002 },	/* General registers.  */	\
   { 0x04000000, 0x00000004 },	/* PSW.  */	\
   { 0xff7fffff, 0x0000001f }	/* All registers.  */		\
@@ -352,7 +352,7 @@ enum reg_class
        && reg_renumber[(REGNO)] <= (MAX)))
 
 #ifdef REG_OK_STRICT
-#define REGNO_OK_FOR_BASE_P(regno)      REGNO_IN_RANGE (regno, 16, 23)
+#define REGNO_OK_FOR_BASE_P(regno)      REGNO_IN_RANGE (regno, 16, 31)
 #else
 #define REGNO_OK_FOR_BASE_P(regno)	1
 #endif

gcc/config/rl78/rl78.opt

@@ -42,6 +42,10 @@ Enum(rl78_mul_types) String(rl78) Value(MUL_RL78)
 EnumValue
 Enum(rl78_mul_types) String(g13) Value(MUL_G13)
 
+mallregs
+Target Mask(ALLREGS)
+Use all registers, reserving none for interrupt handlers.
+
 mrelax
 Target
 Enable assembler and linker relaxation.