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riscv-gcc-1
Commit 09a625f7 by Tom Rix Committed by Tom Rix
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Fix rs6000 -maix64 -mstring 

From-SVN: r47806
parent 0854b1c4
Showing with 93 additions and 5 deletions
gcc/ChangeLog
2001-12-08 Tom Rix <trix@redhat.com>
* config/rs6000/aix43.h (NON_POWERPC_MASKS): Delete MASK_STRING.
* config/rs6000/aix51.h (NON_POWERPC_MASKS): Same.
* config/rs6000/rs6000.md (load_multiple, store_multiple): Do not use
for powerpc64.
* config/rs6000/rs6000.md (movstrsi_8reg, movstrsi_6reg,
movstrsi_4reg, movstrsi_1_reg): Add powerpc64.
* config/rs6000/rs6000.c (expand_block_move): Do not use
gen_movstrsi_2reg and powerpc64.
2001-10-08 Aldy Hernandez <aldyh@redhat.com>
* c-common.h (rid): Add RID_CHOOSE_EXPR and
......
gcc/config/rs6000/aix43.h
......@@ -40,7 +40,7 @@ Boston, MA 02111-1307, USA. */
The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control. */
#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS)) \
......
gcc/config/rs6000/aix51.h
......@@ -40,7 +40,7 @@ Boston, MA 02111-1307, USA. */
The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control. */
#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2)
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS)) \
......
gcc/config/rs6000/rs6000.c
......@@ -4074,7 +4074,7 @@ expand_block_move (operands)
dest_reg, orig_dest),
tmp_reg);
}
else if (bytes > 4)
else if (bytes > 4 && !TARGET_POWERPC64)
{ /* move up to 8 bytes at a time */
move_bytes = (bytes > 8) ? 8 : bytes;
emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
......
gcc/config/rs6000/rs6000.md
......@@ -8568,7 +8568,7 @@
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))])]
"TARGET_STRING"
"TARGET_STRING && !TARGET_POWERPC64"
"
{
int regno;
......@@ -8664,7 +8664,7 @@
(match_operand:SI 1 "" ""))
(clobber (scratch:SI))
(use (match_operand:SI 2 "" ""))])]
"TARGET_STRING"
"TARGET_STRING && !TARGET_POWERPC64"
"
{
int regno;
......@@ -8810,6 +8810,30 @@
[(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
(clobber (reg:SI 6))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
(clobber (reg:SI 9))
(clobber (reg:SI 10))
(clobber (reg:SI 11))
(clobber (reg:SI 12))
(clobber (match_scratch:SI 5 "X"))]
"TARGET_STRING && TARGET_POWERPC64
&& ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
|| INTVAL (operands[2]) == 0)
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 24 bytes at a time. The fixed registers are needed because the
;; register allocator doesn't have a clue about allocating 6 word registers.
;; rD/rS = r5 is preferred, efficient form.
......@@ -8870,6 +8894,27 @@
[(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
(clobber (reg:SI 6))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
(clobber (reg:SI 9))
(clobber (reg:SI 10))
(clobber (match_scratch:SI 5 "X"))]
"TARGET_STRING && TARGET_POWERPC64
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
;; problems with TImode.
;; rD/rS = r5 is preferred, efficient form.
......@@ -8924,6 +8969,25 @@
[(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
(clobber (reg:SI 6))
(clobber (reg:SI 7))
(clobber (reg:SI 8))
(clobber (match_scratch:SI 5 "X"))]
"TARGET_STRING && TARGET_POWERPC64
&& INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
&& (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 8 bytes at a time.
(define_expand "movstrsi_2reg"
[(parallel [(set (match_operand 0 "" "")
......@@ -8998,6 +9062,19 @@
[(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
[(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
(use (match_operand:SI 2 "immediate_operand" "i"))
(use (match_operand:SI 3 "immediate_operand" "i"))
(clobber (match_scratch:SI 4 "=&r"))
(clobber (match_scratch:SI 5 "X"))]
"TARGET_STRING && TARGET_POWERPC64
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
......
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