Commit 0955cf61 by Uros Bizjak

i386.c (option_override_internal): Enable TARGET_CMOVE when TARGET_RDRND is active.

	* config/i386/i386.c (option_override_internal): Enable TARGET_CMOVE
	when TARGET_RDRND is active.
	(ix86_expand_builtin) <case IX86_BUILTIN_RDRAND{16,32,64}_STEP>:
	Generate dummy SImode target register when target is NULL.

From-SVN: r173921
parent 4409de24
2011-05-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (option_override_internal): Enable TARGET_CMOVE
when TARGET_RDRND is active.
(ix86_expand_builtin) <case IX86_BUILTIN_RDRAND{16,32,64}_STEP>:
Generate dummy SImode target register when target is NULL.
2011-05-19 Joseph Myers <joseph@codesourcery.com> 2011-05-19 Joseph Myers <joseph@codesourcery.com>
* config/arm/arm-fpus.def: New. * config/arm/arm-fpus.def: New.
...@@ -59,8 +66,7 @@ ...@@ -59,8 +66,7 @@
Remove ATTRIBUTE_UNUSED. Remove ATTRIBUTE_UNUSED.
[!USE_GAS]: Call solaris_elf_asm_comdat_section for [!USE_GAS]: Call solaris_elf_asm_comdat_section for
SECTION_LINKONCE sections if HAVE_COMDAT_GROUP. SECTION_LINKONCE sections if HAVE_COMDAT_GROUP.
* config/sparc/sparc.c (sparc_solaris_elf_asm_named_section): * config/sparc/sparc.c (sparc_solaris_elf_asm_named_section): Likewise.
Likewise.
* config/i386/sol2-10.h (TARGET_ASM_NAMED_SECTION): Moved ... * config/i386/sol2-10.h (TARGET_ASM_NAMED_SECTION): Moved ...
* config/i386/sol2.h (TARGET_ASM_NAMED_SECTION): ... here. * config/i386/sol2.h (TARGET_ASM_NAMED_SECTION): ... here.
* config/sparc/sol2.h (TARGET_ASM_CODE_END): Redefine. * config/sparc/sol2.h (TARGET_ASM_CODE_END): Redefine.
......
...@@ -4091,8 +4091,9 @@ ix86_option_override_internal (bool main_args_p) ...@@ -4091,8 +4091,9 @@ ix86_option_override_internal (bool main_args_p)
} }
/* For sane SSE instruction set generation we need fcomi instruction. /* For sane SSE instruction set generation we need fcomi instruction.
It is safe to enable all CMOVE instructions. */ It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
if (TARGET_SSE) expands to a sequence that includes conditional move. */
if (TARGET_SSE || TARGET_RDRND)
TARGET_CMOVE = 1; TARGET_CMOVE = 1;
/* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */ /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
...@@ -27613,6 +27614,12 @@ rdrand_step: ...@@ -27613,6 +27614,12 @@ rdrand_step:
op0 = gen_reg_rtx (mode0); op0 = gen_reg_rtx (mode0);
emit_insn (GEN_FCN (icode) (op0)); emit_insn (GEN_FCN (icode) (op0));
arg0 = CALL_EXPR_ARG (exp, 0);
op1 = expand_normal (arg0);
if (!address_operand (op1, VOIDmode))
op1 = copy_addr_to_reg (op1);
emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
op1 = gen_reg_rtx (SImode); op1 = gen_reg_rtx (SImode);
emit_move_insn (op1, CONST1_RTX (SImode)); emit_move_insn (op1, CONST1_RTX (SImode));
...@@ -27627,17 +27634,13 @@ rdrand_step: ...@@ -27627,17 +27634,13 @@ rdrand_step:
else else
op2 = gen_rtx_SUBREG (SImode, op0, 0); op2 = gen_rtx_SUBREG (SImode, op0, 0);
if (target == 0)
target = gen_reg_rtx (SImode);
pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG),
const0_rtx); const0_rtx);
emit_insn (gen_rtx_SET (VOIDmode, op1, emit_insn (gen_rtx_SET (VOIDmode, target,
gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1))); gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1)));
emit_move_insn (target, op1);
arg0 = CALL_EXPR_ARG (exp, 0);
op1 = expand_normal (arg0);
if (!address_operand (op1, VOIDmode))
op1 = copy_addr_to_reg (op1);
emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
return target; return target;
default: default:
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