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riscv-gcc-1
Commit 086c0f96 by Richard Henderson Committed by Richard Henderson
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ia64.md: Use define_constants for unspec numbers. 

        * config/ia64/ia64.md: Use define_constants for unspec numbers.
        * config/ia64/ia64.c: Likewise.

From-SVN: r53344
parent a8b4881f
Showing with 131 additions and 106 deletions
gcc/ChangeLog
2002-05-09 Richard Henderson <rth@redhat.com>
* config/ia64/ia64.md: Use define_constants for unspec numbers.
* config/ia64/ia64.c: Likewise.
2002-05-09 Richard Sandiford <rsandifo@redhat.com> 2002-05-09 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_add_large_offset_to_sp): Remove FILE arg. * config/mips/mips.c (mips_add_large_offset_to_sp): Remove FILE arg.
......
gcc/config/ia64/ia64.c
...@@ -4576,8 +4576,8 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4576,8 +4576,8 @@ rtx_needs_barrier (x, flags, pred)
case UNSPEC: case UNSPEC:
switch (XINT (x, 1)) switch (XINT (x, 1))
{ {
case 1: /* st8.spill */ case UNSPEC_GR_SPILL:
case 2: /* ld8.fill */ case UNSPEC_GR_RESTORE:
{ {
HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1)); HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
HOST_WIDE_INT bit = (offset >> 3) & 63; HOST_WIDE_INT bit = (offset >> 3) & 63;
...@@ -4589,31 +4589,31 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4589,31 +4589,31 @@ rtx_needs_barrier (x, flags, pred)
break; break;
} }
case 3: /* stf.spill */ case UNSPEC_FR_SPILL:
case 4: /* ldf.spill */ case UNSPEC_FR_RESTORE:
case 8: /* popcnt */ case UNSPEC_POPCNT:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
break; break;
case 7: /* pred_rel_mutex */ case UNSPEC_PRED_REL_MUTEX:
case 9: /* pic call */ case UNSPEC_PIC_CALL:
case 12: /* mf */ case UNSPEC_MF:
case 19: /* fetchadd_acq */ case UNSPEC_FETCHADD_ACQ:
case 20: /* mov = ar.bsp */ case UNSPEC_BSP_VALUE:
case 21: /* flushrs */ case UNSPEC_FLUSHRS:
case 22: /* bundle selector */ case UNSPEC_BUNDLE_SELECTOR:
break; break;
case 24: /* addp4 */ case UNSPEC_ADDP4:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
break; break;
case 5: /* recip_approx */ case UNSPEC_FR_RECIP_APPROX:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
break; break;
case 13: /* cmpxchg_acq */ case UNSPEC_CMPXCHG_ACQ:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred); need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
break; break;
...@@ -4626,7 +4626,7 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4626,7 +4626,7 @@ rtx_needs_barrier (x, flags, pred)
case UNSPEC_VOLATILE: case UNSPEC_VOLATILE:
switch (XINT (x, 1)) switch (XINT (x, 1))
{ {
case 0: /* alloc */ case UNSPECV_ALLOC:
/* Alloc must always be the first instruction of a group. /* Alloc must always be the first instruction of a group.
We force this by always returning true. */ We force this by always returning true. */
/* ??? We might get better scheduling if we explicitly check for /* ??? We might get better scheduling if we explicitly check for
...@@ -4640,17 +4640,15 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4640,17 +4640,15 @@ rtx_needs_barrier (x, flags, pred)
rws_access_regno (REG_AR_CFM, new_flags, pred); rws_access_regno (REG_AR_CFM, new_flags, pred);
return 1; return 1;
case 1: /* blockage */ case UNSPECV_SET_BSP:
case 2: /* insn group barrier */
return 0;
case 5: /* set_bsp */
need_barrier = 1; need_barrier = 1;
break; break;
case 7: /* pred.rel.mutex */ case UNSPECV_BLOCKAGE:
case 8: /* safe_across_calls all */ case UNSPECV_INSN_GROUP_BARRIER:
case 9: /* safe_across_calls normal */ case UNSPECV_BREAK:
case UNSPECV_PSAC_ALL:
case UNSPECV_PSAC_NORMAL:
return 0; return 0;
default: default:
...@@ -4877,7 +4875,7 @@ emit_insn_group_barriers (dump, insns) ...@@ -4877,7 +4875,7 @@ emit_insn_group_barriers (dump, insns)
} }
else if (GET_CODE (insn) == INSN else if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
&& XINT (PATTERN (insn), 1) == 2) && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
{ {
init_insn_group_barriers (); init_insn_group_barriers ();
last_label = 0; last_label = 0;
...@@ -6646,7 +6644,7 @@ ia64_emit_nops () ...@@ -6646,7 +6644,7 @@ ia64_emit_nops ()
pat = INSN_P (insn) ? PATTERN (insn) : const0_rtx; pat = INSN_P (insn) ? PATTERN (insn) : const0_rtx;
if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
continue; continue;
if ((GET_CODE (pat) == UNSPEC && XINT (pat, 1) == 22) if ((GET_CODE (pat) == UNSPEC && XINT (pat, 1) == UNSPEC_BUNDLE_SELECTOR)
|| GET_CODE (insn) == CODE_LABEL) || GET_CODE (insn) == CODE_LABEL)
{ {
if (b) if (b)
...@@ -6662,7 +6660,8 @@ ia64_emit_nops () ...@@ -6662,7 +6660,8 @@ ia64_emit_nops ()
bundle_pos = 0; bundle_pos = 0;
continue; continue;
} }
else if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 2) else if (GET_CODE (pat) == UNSPEC_VOLATILE
&& XINT (pat, 1) == UNSPECV_INSN_GROUP_BARRIER)
{ {
int t = INTVAL (XVECEXP (pat, 0, 0)); int t = INTVAL (XVECEXP (pat, 0, 0));
if (b) if (b)
...@@ -6754,7 +6753,7 @@ ia64_reorg (insns) ...@@ -6754,7 +6753,7 @@ ia64_reorg (insns)
insn = prev_active_insn (insn); insn = prev_active_insn (insn);
if (GET_CODE (insn) == INSN if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
&& XINT (PATTERN (insn), 1) == 2) && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
{ {
saw_stop = 1; saw_stop = 1;
insn = prev_active_insn (insn); insn = prev_active_insn (insn);
...@@ -6996,7 +6995,7 @@ process_set (asm_out_file, pat) ...@@ -6996,7 +6995,7 @@ process_set (asm_out_file, pat)
/* Look for the ALLOC insn. */ /* Look for the ALLOC insn. */
if (GET_CODE (src) == UNSPEC_VOLATILE if (GET_CODE (src) == UNSPEC_VOLATILE
&& XINT (src, 1) == 0 && XINT (src, 1) == UNSPECV_ALLOC
&& GET_CODE (dest) == REG) && GET_CODE (dest) == REG)
{ {
dest_regno = REGNO (dest); dest_regno = REGNO (dest);
......
gcc/config/ia64/ia64.md
...@@ -48,34 +48,34 @@ ...@@ -48,34 +48,34 @@
;; ??? Need a better way to describe alternate fp status registers. ;; ??? Need a better way to describe alternate fp status registers.
;; Unspec usage: (define_constants
;; [(UNSPEC_GR_SPILL 1)
;; unspec: (UNSPEC_GR_RESTORE 2)
;; 1 gr_spill (UNSPEC_FR_SPILL 3)
;; 2 gr_restore (UNSPEC_FR_RESTORE 4)
;; 3 fr_spill (UNSPEC_FR_RECIP_APPROX 5)
;; 4 fr_restore (UNSPEC_PRED_REL_MUTEX 7)
;; 5 recip_approx (UNSPEC_POPCNT 8)
;; 7 pred_rel_mutex (UNSPEC_PIC_CALL 9)
;; 8 popcnt (UNSPEC_MF 12)
;; 9 pic call (UNSPEC_CMPXCHG_ACQ 13)
;; 12 mf (UNSPEC_FETCHADD_ACQ 19)
;; 13 cmpxchg_acq (UNSPEC_BSP_VALUE 20)
;; 19 fetchadd_acq (UNSPEC_FLUSHRS 21)
;; 20 bsp_value (UNSPEC_BUNDLE_SELECTOR 22)
;; 21 flushrs (UNSPEC_ADDP4 24)
;; 22 bundle selector (UNSPEC_PROLOGUE_USE 25)
;; 24 addp4 ])
;; 25 prologue_use
;; (define_constants
;; unspec_volatile: [(UNSPECV_ALLOC 0)
;; 0 alloc (UNSPECV_BLOCKAGE 1)
;; 1 blockage (UNSPECV_INSN_GROUP_BARRIER 2)
;; 2 insn_group_barrier (UNSPECV_BREAK 3)
;; 3 break (UNSPECV_SET_BSP 5)
;; 5 set_bsp (UNSPECV_PSAC_ALL 8) ; pred.safe_across_calls
;; 8 pred.safe_across_calls all (UNSPECV_PSAC_NORMAL 9)
;; 9 pred.safe_across_calls normal ])
;; :::::::::::::::::::: ;; ::::::::::::::::::::
;; :: ;; ::
...@@ -261,7 +261,7 @@ ...@@ -261,7 +261,7 @@
&& GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 2) (match_dup 4)) [(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5)) (set (match_dup 3) (match_dup 5))
(set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
...@@ -1288,7 +1288,7 @@ ...@@ -1288,7 +1288,7 @@
(set (match_dup 0) (const_int 1)) (set (match_dup 0) (const_int 1))
(cond_exec (ne (match_dup 2) (const_int 0)) (cond_exec (ne (match_dup 2) (const_int 0))
(set (match_dup 0) (const_int 0))) (set (match_dup 0) (const_int 0)))
(set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
...@@ -1304,7 +1304,7 @@ ...@@ -1304,7 +1304,7 @@
(set (match_dup 0) (const_int 0))) (set (match_dup 0) (const_int 0)))
(cond_exec (eq (match_dup 1) (const_int 0)) (cond_exec (eq (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 1))) (set (match_dup 0) (const_int 1)))
(set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"") "")
(define_insn "*cmpsi_and_0" (define_insn "*cmpsi_and_0"
...@@ -1692,7 +1692,7 @@ ...@@ -1692,7 +1692,7 @@
(set (match_operand:CCI 4 "register_operand" "") (set (match_operand:CCI 4 "register_operand" "")
(match_operand:CCI 5 "register_operand" "")) (match_operand:CCI 5 "register_operand" ""))
(set (match_operand:BI 6 "register_operand" "") (set (match_operand:BI 6 "register_operand" "")
(unspec:BI [(match_dup 6)] 7))] (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
"REGNO (operands[3]) == REGNO (operands[0]) "REGNO (operands[3]) == REGNO (operands[0])
&& REGNO (operands[4]) == REGNO (operands[0]) + 1 && REGNO (operands[4]) == REGNO (operands[0]) + 1
&& REGNO (operands[4]) == REGNO (operands[2]) + 1 && REGNO (operands[4]) == REGNO (operands[2]) + 1
...@@ -2005,7 +2005,8 @@ ...@@ -2005,7 +2005,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0)) (cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
...@@ -2260,7 +2261,7 @@ ...@@ -2260,7 +2261,7 @@
(set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
(set (match_dup 5) (const_int 0)) (set (match_dup 5) (const_int 0))
(set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
(set (match_dup 4) (unspec:DI [(match_dup 3)] 8)) (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_POPCNT))
(set (match_operand:DI 0 "gr_register_operand" "") (set (match_operand:DI 0 "gr_register_operand" "")
(if_then_else:DI (ne (match_dup 6) (const_int 0)) (if_then_else:DI (ne (match_dup 6) (const_int 0))
(match_dup 5) (match_dup 4)))] (match_dup 5) (match_dup 4)))]
...@@ -2276,7 +2277,8 @@ ...@@ -2276,7 +2277,8 @@
(define_insn "*popcnt" (define_insn "*popcnt"
[(set (match_operand:DI 0 "gr_register_operand" "=r") [(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))] (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")]
UNSPEC_POPCNT))]
"" ""
"popcnt %0 = %1" "popcnt %0 = %1"
[(set_attr "itanium_class" "mmmul")]) [(set_attr "itanium_class" "mmmul")])
...@@ -2389,7 +2391,8 @@ ...@@ -2389,7 +2391,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0)) (cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
...@@ -2447,7 +2450,8 @@ ...@@ -2447,7 +2450,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0)) (cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
...@@ -2616,7 +2620,8 @@ ...@@ -2616,7 +2620,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0)) (cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6))) (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
...@@ -2670,7 +2675,8 @@ ...@@ -2670,7 +2675,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0)) (cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
...@@ -2921,7 +2927,8 @@ ...@@ -2921,7 +2927,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9))) [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5)) (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0)) (cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7))) (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
...@@ -2998,7 +3005,8 @@ ...@@ -2998,7 +3005,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0)) (cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
...@@ -3394,7 +3402,8 @@ ...@@ -3394,7 +3402,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 7) (const_int 0)) (cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
...@@ -3471,7 +3480,8 @@ ...@@ -3471,7 +3480,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))]) (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0)) (cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (parallel [(set (match_dup 3)
...@@ -3545,7 +3555,7 @@ ...@@ -3545,7 +3555,7 @@
(match_operand:TF 3 "fr_register_operand" "f"))) (match_operand:TF 3 "fr_register_operand" "f")))
(set (match_operand:BI 1 "register_operand" "=c") (set (match_operand:BI 1 "register_operand" "=c")
(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f") (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
(match_dup 3)] 5)) (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))] (use (match_operand:SI 4 "const_int_operand" ""))]
"INTEL_EXTENDED_IEEE_FORMAT" "INTEL_EXTENDED_IEEE_FORMAT"
"frcpa.s%4 %0, %1 = %2, %3" "frcpa.s%4 %0, %1 = %2, %3"
...@@ -4682,7 +4692,7 @@ ...@@ -4682,7 +4692,7 @@
(define_insn "call_pic" (define_insn "call_pic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
(match_operand 1 "" "")) (match_operand 1 "" ""))
(use (unspec [(reg:DI 1)] 9)) (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
(clobber (match_operand:DI 2 "register_operand" "=b,b"))] (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
"" ""
"br.call%+.many %2 = %0" "br.call%+.many %2 = %0"
...@@ -4692,7 +4702,7 @@ ...@@ -4692,7 +4702,7 @@
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(use (unspec [(reg:DI 1)] 9)) (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
(clobber (match_operand:DI 3 "register_operand" "=b,b"))] (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
"" ""
"br.call%+.many %3 = %1" "br.call%+.many %3 = %1"
...@@ -4701,7 +4711,7 @@ ...@@ -4701,7 +4711,7 @@
(define_insn "sibcall_pic" (define_insn "sibcall_pic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "bi")) [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
(match_operand 1 "" "")) (match_operand 1 "" ""))
(use (unspec [(reg:DI 1)] 9)) (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
(use (match_operand:DI 2 "register_operand" "=b")) (use (match_operand:DI 2 "register_operand" "=b"))
(use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))]
"" ""
...@@ -4871,7 +4881,7 @@ ...@@ -4871,7 +4881,7 @@
(define_insn "alloc" (define_insn "alloc"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(const_int 0)] 0)) (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
(use (match_operand:DI 1 "const_int_operand" "i")) (use (match_operand:DI 1 "const_int_operand" "i"))
(use (match_operand:DI 2 "const_int_operand" "i")) (use (match_operand:DI 2 "const_int_operand" "i"))
(use (match_operand:DI 3 "const_int_operand" "i")) (use (match_operand:DI 3 "const_int_operand" "i"))
...@@ -4885,7 +4895,8 @@ ...@@ -4885,7 +4895,8 @@
(define_expand "gr_spill" (define_expand "gr_spill"
[(parallel [(set (match_operand:DI 0 "memory_operand" "=m") [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const_int_operand" "")] 1)) (match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_SPILL))
(clobber (match_dup 3))])] (clobber (match_dup 3))])]
"" ""
"operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
...@@ -4893,7 +4904,8 @@ ...@@ -4893,7 +4904,8 @@
(define_insn "gr_spill_internal" (define_insn "gr_spill_internal"
[(set (match_operand:DI 0 "memory_operand" "=m") [(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const_int_operand" "")] 1)) (match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_SPILL))
(clobber (match_operand:DI 3 "register_operand" ""))] (clobber (match_operand:DI 3 "register_operand" ""))]
"" ""
"* "*
...@@ -4906,7 +4918,8 @@ ...@@ -4906,7 +4918,8 @@
(define_expand "gr_restore" (define_expand "gr_restore"
[(parallel [(set (match_operand:DI 0 "register_operand" "=r") [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m") (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
(match_operand:DI 2 "const_int_operand" "")] 2)) (match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_RESTORE))
(use (match_dup 3))])] (use (match_dup 3))])]
"" ""
"operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
...@@ -4914,7 +4927,8 @@ ...@@ -4914,7 +4927,8 @@
(define_insn "gr_restore_internal" (define_insn "gr_restore_internal"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m") (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
(match_operand:DI 2 "const_int_operand" "")] 2)) (match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_RESTORE))
(use (match_operand:DI 3 "register_operand" ""))] (use (match_operand:DI 3 "register_operand" ""))]
"" ""
"* "*
...@@ -4925,14 +4939,16 @@ ...@@ -4925,14 +4939,16 @@
(define_insn "fr_spill" (define_insn "fr_spill"
[(set (match_operand:TF 0 "memory_operand" "=m") [(set (match_operand:TF 0 "memory_operand" "=m")
(unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))] (unspec:TF [(match_operand:TF 1 "register_operand" "f")]
UNSPEC_FR_SPILL))]
"" ""
"stf.spill %0 = %1%P0" "stf.spill %0 = %1%P0"
[(set_attr "itanium_class" "stf")]) [(set_attr "itanium_class" "stf")])
(define_insn "fr_restore" (define_insn "fr_restore"
[(set (match_operand:TF 0 "register_operand" "=f") [(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))] (unspec:TF [(match_operand:TF 1 "memory_operand" "m")]
UNSPEC_FR_RESTORE))]
"" ""
"ldf.fill %0 = %1%P1" "ldf.fill %0 = %1%P1"
[(set_attr "itanium_class" "fld")]) [(set_attr "itanium_class" "fld")])
...@@ -4943,13 +4959,14 @@ ...@@ -4943,13 +4959,14 @@
(define_insn "bsp_value" (define_insn "bsp_value"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] 20))] (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
"" ""
";;\;mov %0 = ar.bsp" ";;\;mov %0 = ar.bsp"
[(set_attr "itanium_class" "frar_i")]) [(set_attr "itanium_class" "frar_i")])
(define_insn "set_bsp" (define_insn "set_bsp"
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)] [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
UNSPECV_SET_BSP)]
"" ""
"flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19" "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
[(set_attr "itanium_class" "unknown") [(set_attr "itanium_class" "unknown")
...@@ -4960,7 +4977,7 @@ ...@@ -4960,7 +4977,7 @@
;; fixed later. This avoids an RSE DV. ;; fixed later. This avoids an RSE DV.
(define_insn "flushrs" (define_insn "flushrs"
[(unspec [(const_int 0)] 21)] [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
"" ""
";;\;flushrs\;;;" ";;\;flushrs\;;;"
[(set_attr "itanium_class" "rse_m")]) [(set_attr "itanium_class" "rse_m")])
...@@ -5012,7 +5029,7 @@ ...@@ -5012,7 +5029,7 @@
[(set_attr "itanium_class" "nop_x")]) [(set_attr "itanium_class" "nop_x")])
(define_insn "bundle_selector" (define_insn "bundle_selector"
[(unspec [(match_operand 0 "const_int_operand" "")] 22)] [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
"" ""
"* "*
{ {
...@@ -5024,14 +5041,15 @@ ...@@ -5024,14 +5041,15 @@
;; Pseudo instruction that prevents the scheduler from moving code above this ;; Pseudo instruction that prevents the scheduler from moving code above this
;; point. ;; point.
(define_insn "blockage" (define_insn "blockage"
[(unspec_volatile [(const_int 0)] 1)] [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
"" ""
"" ""
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
(define_insn "insn_group_barrier" (define_insn "insn_group_barrier"
[(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)] [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
UNSPECV_INSN_GROUP_BARRIER)]
"" ""
";;" ";;"
[(set_attr "itanium_class" "stop_bit") [(set_attr "itanium_class" "stop_bit")
...@@ -5069,7 +5087,7 @@ ...@@ -5069,7 +5087,7 @@
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
(define_insn "break_f" (define_insn "break_f"
[(unspec_volatile [(const_int 0)] 3)] [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
"" ""
"break.f 0" "break.f 0"
[(set_attr "itanium_class" "nop_f")]) [(set_attr "itanium_class" "nop_f")])
...@@ -5204,7 +5222,7 @@ ...@@ -5204,7 +5222,7 @@
(define_expand "mf" (define_expand "mf"
[(set (mem:BLK (match_dup 0)) [(set (mem:BLK (match_dup 0))
(unspec:BLK [(mem:BLK (match_dup 0))] 12))] (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
"" ""
" "
{ {
...@@ -5214,7 +5232,7 @@ ...@@ -5214,7 +5232,7 @@
(define_insn "*mf_internal" (define_insn "*mf_internal"
[(set (match_operand:BLK 0 "" "") [(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:BLK 1 "" "")] 12))] (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
"" ""
"mf" "mf"
[(set_attr "itanium_class" "syst_m")]) [(set_attr "itanium_class" "syst_m")])
...@@ -5224,7 +5242,8 @@ ...@@ -5224,7 +5242,8 @@
(match_dup 1)) (match_dup 1))
(set (match_operand:SI 1 "not_postinc_memory_operand" "+S") (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
(unspec:SI [(match_dup 1) (unspec:SI [(match_dup 1)
(match_operand:SI 2 "fetchadd_operand" "n")] 19))] (match_operand:SI 2 "fetchadd_operand" "n")]
UNSPEC_FETCHADD_ACQ))]
"" ""
"fetchadd4.acq %0 = %1, %2" "fetchadd4.acq %0 = %1, %2"
[(set_attr "itanium_class" "sem")]) [(set_attr "itanium_class" "sem")])
...@@ -5234,7 +5253,8 @@ ...@@ -5234,7 +5253,8 @@
(match_dup 1)) (match_dup 1))
(set (match_operand:DI 1 "not_postinc_memory_operand" "+S") (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
(unspec:DI [(match_dup 1) (unspec:DI [(match_dup 1)
(match_operand:DI 2 "fetchadd_operand" "n")] 19))] (match_operand:DI 2 "fetchadd_operand" "n")]
UNSPEC_FETCHADD_ACQ))]
"" ""
"fetchadd8.acq %0 = %1, %2" "fetchadd8.acq %0 = %1, %2"
[(set_attr "itanium_class" "sem")]) [(set_attr "itanium_class" "sem")])
...@@ -5245,7 +5265,8 @@ ...@@ -5245,7 +5265,8 @@
(set (match_operand:SI 1 "not_postinc_memory_operand" "+S") (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
(unspec:SI [(match_dup 1) (unspec:SI [(match_dup 1)
(match_operand:SI 2 "gr_register_operand" "r") (match_operand:SI 2 "gr_register_operand" "r")
(match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))] (match_operand:SI 3 "ar_ccv_reg_operand" "")]
UNSPEC_CMPXCHG_ACQ))]
"" ""
"cmpxchg4.acq %0 = %1, %2, %3" "cmpxchg4.acq %0 = %1, %2, %3"
[(set_attr "itanium_class" "sem")]) [(set_attr "itanium_class" "sem")])
...@@ -5256,7 +5277,8 @@ ...@@ -5256,7 +5277,8 @@
(set (match_operand:DI 1 "not_postinc_memory_operand" "+S") (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
(unspec:DI [(match_dup 1) (unspec:DI [(match_dup 1)
(match_operand:DI 2 "gr_register_operand" "r") (match_operand:DI 2 "gr_register_operand" "r")
(match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))] (match_operand:DI 3 "ar_ccv_reg_operand" "")]
UNSPEC_CMPXCHG_ACQ))]
"" ""
"cmpxchg8.acq %0 = %1, %2, %3" "cmpxchg8.acq %0 = %1, %2, %3"
[(set_attr "itanium_class" "sem")]) [(set_attr "itanium_class" "sem")])
...@@ -5290,21 +5312,21 @@ ...@@ -5290,21 +5312,21 @@
(define_insn "pred_rel_mutex" (define_insn "pred_rel_mutex"
[(set (match_operand:BI 0 "register_operand" "+c") [(set (match_operand:BI 0 "register_operand" "+c")
(unspec:BI [(match_dup 0)] 7))] (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"" ""
".pred.rel.mutex %0, %I0" ".pred.rel.mutex %0, %I0"
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
(define_insn "safe_across_calls_all" (define_insn "safe_across_calls_all"
[(unspec_volatile [(const_int 0)] 8)] [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
"" ""
".pred.safe_across_calls p1-p63" ".pred.safe_across_calls p1-p63"
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
(define_insn "safe_across_calls_normal" (define_insn "safe_across_calls_normal"
[(unspec_volatile [(const_int 0)] 9)] [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
"" ""
"* "*
{ {
...@@ -5314,14 +5336,13 @@ ...@@ -5314,14 +5336,13 @@
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
;;
;;
;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
;; pointer. This is used by the HP-UX 32 bit mode. ;; pointer. This is used by the HP-UX 32 bit mode.
(define_insn "ptr_extend" (define_insn "ptr_extend"
[(set (match_operand:DI 0 "gr_register_operand" "=r") [(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] 24))] (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
UNSPEC_ADDP4))]
"" ""
"addp4 %0 = 0,%1" "addp4 %0 = 0,%1"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
...@@ -5334,7 +5355,7 @@ ...@@ -5334,7 +5355,7 @@
(unspec:DI (unspec:DI
[(plus:SI (match_operand:SI 1 "basereg_operand" "r") [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
(match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
24))] UNSPEC_ADDP4))]
"" ""
"addp4 %0 = %2, %1" "addp4 %0 = %2, %1"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
...@@ -5344,16 +5365,16 @@ ...@@ -5344,16 +5365,16 @@
(unspec:DI (unspec:DI
[(plus:SI (match_operand:SI 1 "gr_register_operand" "r") [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
(match_operand:SI 2 "basereg_operand" "r"))] (match_operand:SI 2 "basereg_operand" "r"))]
24))] UNSPEC_ADDP4))]
"" ""
"addp4 %0 = %1, %2" "addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")]) [(set_attr "itanium_class" "ialu")])
;;
;; As USE insns aren't meaningful after reload, this is used instead ;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling ;; to prevent deleting instructions setting registers for EH handling
(define_insn "prologue_use" (define_insn "prologue_use"
[(unspec:DI [(match_operand:DI 0 "register_operand" "")] 25)] [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
UNSPEC_PROLOGUE_USE)]
"" ""
"// %0 needed for EH" "// %0 needed for EH"
[(set_attr "itanium_class" "ignore") [(set_attr "itanium_class" "ignore")
......
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