Commit 086c0f96 by Richard Henderson Committed by Richard Henderson

ia64.md: Use define_constants for unspec numbers.

        * config/ia64/ia64.md: Use define_constants for unspec numbers.
        * config/ia64/ia64.c: Likewise.

From-SVN: r53344
parent a8b4881f
2002-05-09 Richard Henderson <rth@redhat.com>
* config/ia64/ia64.md: Use define_constants for unspec numbers.
* config/ia64/ia64.c: Likewise.
2002-05-09 Richard Sandiford <rsandifo@redhat.com> 2002-05-09 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_add_large_offset_to_sp): Remove FILE arg. * config/mips/mips.c (mips_add_large_offset_to_sp): Remove FILE arg.
......
...@@ -4576,8 +4576,8 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4576,8 +4576,8 @@ rtx_needs_barrier (x, flags, pred)
case UNSPEC: case UNSPEC:
switch (XINT (x, 1)) switch (XINT (x, 1))
{ {
case 1: /* st8.spill */ case UNSPEC_GR_SPILL:
case 2: /* ld8.fill */ case UNSPEC_GR_RESTORE:
{ {
HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1)); HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
HOST_WIDE_INT bit = (offset >> 3) & 63; HOST_WIDE_INT bit = (offset >> 3) & 63;
...@@ -4589,31 +4589,31 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4589,31 +4589,31 @@ rtx_needs_barrier (x, flags, pred)
break; break;
} }
case 3: /* stf.spill */ case UNSPEC_FR_SPILL:
case 4: /* ldf.spill */ case UNSPEC_FR_RESTORE:
case 8: /* popcnt */ case UNSPEC_POPCNT:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
break; break;
case 7: /* pred_rel_mutex */ case UNSPEC_PRED_REL_MUTEX:
case 9: /* pic call */ case UNSPEC_PIC_CALL:
case 12: /* mf */ case UNSPEC_MF:
case 19: /* fetchadd_acq */ case UNSPEC_FETCHADD_ACQ:
case 20: /* mov = ar.bsp */ case UNSPEC_BSP_VALUE:
case 21: /* flushrs */ case UNSPEC_FLUSHRS:
case 22: /* bundle selector */ case UNSPEC_BUNDLE_SELECTOR:
break; break;
case 24: /* addp4 */ case UNSPEC_ADDP4:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
break; break;
case 5: /* recip_approx */ case UNSPEC_FR_RECIP_APPROX:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
break; break;
case 13: /* cmpxchg_acq */ case UNSPEC_CMPXCHG_ACQ:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred); need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
break; break;
...@@ -4626,7 +4626,7 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4626,7 +4626,7 @@ rtx_needs_barrier (x, flags, pred)
case UNSPEC_VOLATILE: case UNSPEC_VOLATILE:
switch (XINT (x, 1)) switch (XINT (x, 1))
{ {
case 0: /* alloc */ case UNSPECV_ALLOC:
/* Alloc must always be the first instruction of a group. /* Alloc must always be the first instruction of a group.
We force this by always returning true. */ We force this by always returning true. */
/* ??? We might get better scheduling if we explicitly check for /* ??? We might get better scheduling if we explicitly check for
...@@ -4640,17 +4640,15 @@ rtx_needs_barrier (x, flags, pred) ...@@ -4640,17 +4640,15 @@ rtx_needs_barrier (x, flags, pred)
rws_access_regno (REG_AR_CFM, new_flags, pred); rws_access_regno (REG_AR_CFM, new_flags, pred);
return 1; return 1;
case 1: /* blockage */ case UNSPECV_SET_BSP:
case 2: /* insn group barrier */
return 0;
case 5: /* set_bsp */
need_barrier = 1; need_barrier = 1;
break; break;
case 7: /* pred.rel.mutex */ case UNSPECV_BLOCKAGE:
case 8: /* safe_across_calls all */ case UNSPECV_INSN_GROUP_BARRIER:
case 9: /* safe_across_calls normal */ case UNSPECV_BREAK:
case UNSPECV_PSAC_ALL:
case UNSPECV_PSAC_NORMAL:
return 0; return 0;
default: default:
...@@ -4877,7 +4875,7 @@ emit_insn_group_barriers (dump, insns) ...@@ -4877,7 +4875,7 @@ emit_insn_group_barriers (dump, insns)
} }
else if (GET_CODE (insn) == INSN else if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
&& XINT (PATTERN (insn), 1) == 2) && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
{ {
init_insn_group_barriers (); init_insn_group_barriers ();
last_label = 0; last_label = 0;
...@@ -6646,7 +6644,7 @@ ia64_emit_nops () ...@@ -6646,7 +6644,7 @@ ia64_emit_nops ()
pat = INSN_P (insn) ? PATTERN (insn) : const0_rtx; pat = INSN_P (insn) ? PATTERN (insn) : const0_rtx;
if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
continue; continue;
if ((GET_CODE (pat) == UNSPEC && XINT (pat, 1) == 22) if ((GET_CODE (pat) == UNSPEC && XINT (pat, 1) == UNSPEC_BUNDLE_SELECTOR)
|| GET_CODE (insn) == CODE_LABEL) || GET_CODE (insn) == CODE_LABEL)
{ {
if (b) if (b)
...@@ -6662,7 +6660,8 @@ ia64_emit_nops () ...@@ -6662,7 +6660,8 @@ ia64_emit_nops ()
bundle_pos = 0; bundle_pos = 0;
continue; continue;
} }
else if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 2) else if (GET_CODE (pat) == UNSPEC_VOLATILE
&& XINT (pat, 1) == UNSPECV_INSN_GROUP_BARRIER)
{ {
int t = INTVAL (XVECEXP (pat, 0, 0)); int t = INTVAL (XVECEXP (pat, 0, 0));
if (b) if (b)
...@@ -6754,7 +6753,7 @@ ia64_reorg (insns) ...@@ -6754,7 +6753,7 @@ ia64_reorg (insns)
insn = prev_active_insn (insn); insn = prev_active_insn (insn);
if (GET_CODE (insn) == INSN if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
&& XINT (PATTERN (insn), 1) == 2) && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
{ {
saw_stop = 1; saw_stop = 1;
insn = prev_active_insn (insn); insn = prev_active_insn (insn);
...@@ -6996,7 +6995,7 @@ process_set (asm_out_file, pat) ...@@ -6996,7 +6995,7 @@ process_set (asm_out_file, pat)
/* Look for the ALLOC insn. */ /* Look for the ALLOC insn. */
if (GET_CODE (src) == UNSPEC_VOLATILE if (GET_CODE (src) == UNSPEC_VOLATILE
&& XINT (src, 1) == 0 && XINT (src, 1) == UNSPECV_ALLOC
&& GET_CODE (dest) == REG) && GET_CODE (dest) == REG)
{ {
dest_regno = REGNO (dest); dest_regno = REGNO (dest);
......
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