Skip to content

R
riscv-gcc-1
Commit 0826f1d8 by Jeffrey A Law Committed by Jeff Law
Options

toplev.c (dump_file_index): Move SSA dumps just after first jump dump. 

       * toplev.c (dump_file_index): Move SSA dumps just after first
        jump dump.
        (dump_file): Corresponding changes.
        (rest_of_compilation): Move SSA path to just after the first
        jump pass.
        * doc/gcc.texi (Passes): Update due to movement of SSA path.
        * doc/invoke.texi: Update dump file #s as they were completely
        out of date with reality.

From-SVN: r43704
parent 918a6124
Showing with 117 additions and 97 deletions
gcc/ChangeLog
Mon Jul 2 14:20:13 2001 Jeffrey A Law (law@cygnus.com)
* toplev.c (dump_file_index): Move SSA dumps just after first
jump dump.
(dump_file): Corresponding changes.
(rest_of_compilation): Move SSA path to just after the first
jump pass.
* doc/gcc.texi (Passes): Update due to movement of SSA path.
* doc/invoke.texi: Update dump file #s as they were completely
out of date with reality.
2001-07-02 Geoffrey Keating <geoffk@redhat.com>
* doc/tm.texi (Frame Layout): Document STACK_PUSH_CODE.
......
gcc/doc/gcc.texi
......@@ -3372,6 +3372,7 @@ The option @option{-dj} causes a debugging dump of the RTL code after
this pass is run for the first time. This dump file's name is made by
appending @samp{.jump} to the input file name.
@cindex register use analysis
@item
Register scan. This pass finds the first and last use of each
......@@ -3387,20 +3388,6 @@ the second conditional test. The source code for this pass is in
@file{jump.c}. This optimization is only performed if
@option{-fthread-jumps} is enabled.
@cindex common subexpression elimination
@cindex constant propagation
@item
Common subexpression elimination. This pass also does constant
propagation. Its source files are @file{cse.c}, and @file{cselib.c}.
If constant propagation causes conditional jumps to become
unconditional or to become no-ops, jump optimization is run again when
CSE is finished.
@opindex ds
The option @option{-ds} causes a debugging dump of the RTL code after
this pass. This dump file's name is made by appending @samp{.cse} to
the input file name.
@cindex SSA optimizations
@cindex Single Static Assignment optimizations
@opindex fssa
......@@ -3435,6 +3422,21 @@ The option @option{-dX} causes a debugging dump of the RTL code after
this pass. This dump file's name is made by appending @samp{.ssadce} to
the input file name.
@end itemize
@cindex common subexpression elimination
@cindex constant propagation
@item
Common subexpression elimination. This pass also does constant
propagation. Its source files are @file{cse.c}, and @file{cselib.c}.
If constant propagation causes conditional jumps to become
unconditional or to become no-ops, jump optimization is run again when
CSE is finished.
@opindex ds
The option @option{-ds} causes a debugging dump of the RTL code after
this pass. This dump file's name is made by appending @samp{.cse} to
the input file name.
@cindex global common subexpression elimination
@cindex constant propagation
@cindex copy propagation
......
gcc/doc/invoke.texi
......@@ -2856,101 +2856,105 @@ Here are the possible letters for use in @var{letters}, and their meanings:
Annotate the assembler output with miscellaneous debugging information.
@item b
@opindex db
Dump after computing branch probabilities, to @file{@var{file}.11.bp}.
Dump after computing branch probabilities, to @file{@var{file}.13.bp}.
@item B
@opindex dB
Dump after block reordering, to @file{@var{file}.26.bbro}.
Dump after block reordering, to @file{@var{file}.27.bbro}.
@item c
@opindex dc
Dump after instruction combination, to the file @file{@var{file}.14.combine}.
Dump after instruction combination, to the file @file{@var{file}.15.combine}.
@item C
@opindex dC
Dump after the first if conversion, to the file @file{@var{file}.15.ce}.
Dump after the first if conversion, to the file @file{@var{file}.16.ce}.
@item d
@opindex dd
Dump after delayed branch scheduling, to @file{@var{file}.29.dbr}.
Dump after delayed branch scheduling, to @file{@var{file}.30.dbr}.
@item D
@opindex dD
Dump all macro definitions, at the end of preprocessing, in addition to
normal output.
@item e
@opindex de
Dump after SSA optimizations, to @file{@var{file}.05.ssa} and
Dump after SSA optimizations, to @file{@var{file}.04.ssa} and
@file{@var{file}.06.ussa}.
@item E
@opindex dE
Dump after the second if conversion, to @file{@var{file}.24.ce2}.
Dump after the second if conversion, to @file{@var{file}.25.ce2}.
@item f
@opindex df
Dump after life analysis, to @file{@var{file}.13.life}.
Dump after life analysis, to @file{@var{file}.14.life}.
@item F
@opindex dF
Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.04.addressof}.
Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.08.addressof}.
@item g
@opindex dg
Dump after global register allocation, to @file{@var{file}.19.greg}.
Dump after global register allocation, to @file{@var{file}.20.greg}.
@item h
@opindex dh
Dump after finalization of EH handling code, to @file{@var{file}.02.eh}.
@item o
@item o
@opindex do
Dump after post-reload CSE and other optimizations, to @file{@var{file}.20.postreload}.
Dump after post-reload CSE and other optimizations, to @file{@var{file}.21.postreload}.
@item G
@opindex dG
Dump after GCSE, to @file{@var{file}.08.gcse}.
Dump after GCSE, to @file{@var{file}.09.gcse}.
@item i
@opindex di
Dump after sibling call optimizations, to @file{@var{file}.01.sibling}.
@item j
@opindex dj
Dump after the first jump optimization, to @file{@var{file}.02.jump}.
Dump after the first jump optimization, to @file{@var{file}.03.jump}.
@item J
@opindex dJ
Dump after the last jump optimization, to @file{@var{file}.27.jump2}.
Dump after the last jump optimization, to @file{@var{file}.28.jump2}.
@item k
@opindex dk
Dump after conversion from registers to stack, to @file{@var{file}.29.stack}.
Dump after conversion from registers to stack, to @file{@var{file}.31.stack}.
@item l
@opindex dl
Dump after local register allocation, to @file{@var{file}.18.lreg}.
Dump after local register allocation, to @file{@var{file}.19.lreg}.
@item L
@opindex dL
Dump after loop optimization, to @file{@var{file}.09.loop}.
Dump after loop optimization, to @file{@var{file}.10.loop}.
@item M
@opindex dM
Dump after performing the machine dependent reorganisation pass, to
@file{@var{file}.28.mach}.
@file{@var{file}.29.mach}.
@item n
@opindex dn
Dump after register renumbering, to @file{@var{file}.23.rnreg}.
Dump after register renumbering, to @file{@var{file}.24.rnreg}.
@item N
@opindex dN
Dump after the register move pass, to @file{@var{file}.16.regmove}.
Dump after the register move pass, to @file{@var{file}.17.regmove}.
@item r
@opindex dr
Dump after RTL generation, to @file{@var{file}.00.rtl}.
@item R
@opindex dR
Dump after the second instruction scheduling pass, to
@file{@var{file}.25.sched2}.
@file{@var{file}.26.sched2}.
@item s
@opindex ds
Dump after CSE (including the jump optimization that sometimes follows
CSE), to @file{@var{file}.03.cse}.
CSE), to @file{@var{file}.07.cse}.
@item S
@opindex dS
Dump after the first instruction scheduling pass, to
@file{@var{file}.17.sched}.
@file{@var{file}.18.sched}.
@item t
@opindex dt
Dump after the second CSE pass (including the jump optimization that
sometimes follows CSE), to @file{@var{file}.10.cse2}.
sometimes follows CSE), to @file{@var{file}.11.cse2}.
@item w
@opindex dw
Dump after the second flow pass, to @file{@var{file}.21.flow2}.
Dump after the second flow pass, to @file{@var{file}.22.flow2}.
@item X
@opindex dX
Dump after SSA aggressive dead code elimination, to @file{@var{file}.06.ssadce}.
Dump after SSA aggressive dead code elimination, to @file{@var{file}.05.ssadce}.
@item z
@opindex dz
Dump after the peephole pass, to @file{@var{file}.22.peephole2}.
Dump after the peephole pass, to @file{@var{file}.23.peephole2}.
@item a
@opindex da
Produce all the dumps listed above.
......
gcc/toplev.c
......@@ -253,11 +253,11 @@ enum dump_file_index
DFI_sibling,
DFI_eh,
DFI_jump,
DFI_cse,
DFI_addressof,
DFI_ssa,
DFI_ssa_dce,
DFI_ussa,
DFI_cse,
DFI_addressof,
DFI_gcse,
DFI_loop,
DFI_cse2,
......@@ -299,11 +299,11 @@ struct dump_file_info dump_file[DFI_MAX] =
{ "sibling", 'i', 0, 0, 0 },
{ "eh", 'h', 0, 0, 0 },
{ "jump", 'j', 0, 0, 0 },
{ "cse", 's', 0, 0, 0 },
{ "addressof", 'F', 0, 0, 0 },
{ "ssa", 'e', 1, 0, 0 },
{ "ssadce", 'X', 1, 0, 0 },
{ "ussa", 'e', 1, 0, 0 }, /* Yes, duplicate enable switch. */
{ "cse", 's', 0, 0, 0 },
{ "addressof", 'F', 0, 0, 0 },
{ "gcse", 'G', 1, 0, 0 },
{ "loop", 'L', 1, 0, 0 },
{ "cse2", 't', 1, 0, 0 },
......@@ -2947,6 +2947,61 @@ rest_of_compilation (decl)
goto exit_rest_of_compilation;
}
/* Long term, this should probably move before the jump optimizer too,
but I didn't want to disturb the rtl_dump_and_exit and related
stuff at this time. */
if (optimize > 0 && flag_ssa)
{
/* Convert to SSA form. */
timevar_push (TV_TO_SSA);
open_dump_file (DFI_ssa, decl);
find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
cleanup_cfg ();
convert_to_ssa ();
close_dump_file (DFI_ssa, print_rtl_with_bb, insns);
timevar_pop (TV_TO_SSA);
/* The SSA implementation uses basic block numbers in its phi
nodes. Thus, changing the control-flow graph or the basic
blocks, e.g., calling find_basic_blocks () or cleanup_cfg (),
may cause problems. */
if (flag_ssa_dce)
{
/* Remove dead code. */
timevar_push (TV_SSA_DCE);
open_dump_file (DFI_ssa_dce, decl);
insns = get_insns ();
ssa_eliminate_dead_code();
close_dump_file (DFI_ssa_dce, print_rtl_with_bb, insns);
timevar_pop (TV_SSA_DCE);
}
/* Convert from SSA form. */
timevar_push (TV_FROM_SSA);
open_dump_file (DFI_ussa, decl);
convert_from_ssa ();
/* New registers have been created. Rescan their usage. */
reg_scan (insns, max_reg_num (), 1);
/* Life analysis used in SSA adds log_links but these
shouldn't be there until the flow stage, so clear
them away. */
clear_log_links (insns);
close_dump_file (DFI_ussa, print_rtl_with_bb, insns);
timevar_pop (TV_FROM_SSA);
ggc_collect ();
}
timevar_push (TV_JUMP);
if (optimize > 0)
......@@ -3045,58 +3100,6 @@ rest_of_compilation (decl)
ggc_collect ();
if (optimize > 0 && flag_ssa)
{
/* Convert to SSA form. */
timevar_push (TV_TO_SSA);
open_dump_file (DFI_ssa, decl);
find_basic_blocks (insns, max_reg_num (), rtl_dump_file);
cleanup_cfg ();
convert_to_ssa ();
close_dump_file (DFI_ssa, print_rtl_with_bb, insns);
timevar_pop (TV_TO_SSA);
/* The SSA implementation uses basic block numbers in its phi
nodes. Thus, changing the control-flow graph or the basic
blocks, e.g., calling find_basic_blocks () or cleanup_cfg (),
may cause problems. */
if (flag_ssa_dce)
{
/* Remove dead code. */
timevar_push (TV_SSA_DCE);
open_dump_file (DFI_ssa_dce, decl);
insns = get_insns ();
ssa_eliminate_dead_code();
close_dump_file (DFI_ssa_dce, print_rtl_with_bb, insns);
timevar_pop (TV_SSA_DCE);
}
/* Convert from SSA form. */
timevar_push (TV_FROM_SSA);
open_dump_file (DFI_ussa, decl);
convert_from_ssa ();
/* New registers have been created. Rescan their usage. */
reg_scan (insns, max_reg_num (), 1);
/* Life analysis used in SSA adds log_links but these
shouldn't be there until the flow stage, so clear
them away. */
clear_log_links (insns);
close_dump_file (DFI_ussa, print_rtl_with_bb, insns);
timevar_pop (TV_FROM_SSA);
ggc_collect ();
}
/* Perform global cse. */
if (optimize > 0 && flag_gcse)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment