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riscv-gcc-1
Commit 0774c160 by Alexander Ivchenko Committed by Kirill Yukhin
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AVX-512. Extend extract insn patterns. 

gcc/
	* config/i386/i386.c
	(ix86_expand_vector_extract): Handle V32HI and V64QI modes.
	* config/i386/sse.md
	(define_mode_iterator VI48F_256): New.
	(define_mode_attr extract_type): Ditto.
	(define_mode_attr extract_suf): Ditto.
	(define_mode_iterator AVX512_VEC): Ditto.
	(define_expand
	"<extract_type>_vextract<shuffletype><extract_suf>_mask"): Use
	AVX512_VEC.
	(define_insn "avx512dq_vextract<shuffletype>64x2_1_maskm"): New.
	(define_insn
	"<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>"):
	Ditto.
	(define_mode_attr extract_type_2): Ditto.
	(define_mode_attr extract_suf_2): Ditto.
	(define_mode_iterator AVX512_VEC_2): Ditto.
	(define_expand
	"<extract_type_2>_vextract<shuffletype><extract_suf_2>_mask"): Use
	AVX512_VEC_2 mode iterator.
	(define_insn "vec_extract_hi_<mode>_maskm"): Ditto.
	(define_expand "avx512vl_vextractf128<mode>"): Ditto.
	(define_insn_and_split "vec_extract_lo_<mode>"): Delete.
	(define_insn "vec_extract_lo_<mode><mask_name>"): New.
	(define_split for V16FI mode): Ditto.
	(define_insn_and_split "vec_extract_lo_<mode>"): Delete.
	(define_insn "vec_extract_lo_<mode><mask_name>"): New.
	(define_split for VI8F_256 mode): Ditto.
	(define_insn "vec_extract_hi_<mode><mask_name>"): Add masking.
	(define_insn_and_split "vec_extract_lo_<mode>"): Delete.
	(define_insn "vec_extract_lo_<mode><mask_name>"): New.
	(define_split for VI4F_256 mode): Ditto.
	(define_insn "vec_extract_lo_<mode>_maskm"): Ditto.
	(define_insn "vec_extract_hi_<mode>_maskm"): Ditto.
	(define_insn "vec_extract_hi_<mode><mask_name>"): Add masking.
	(define_mode_iterator VEC_EXTRACT_MODE): Add V64QI and V32HI modes.
	(define_insn "vcvtph2ps<mask_name>"): Fix pattern condition.
	(define_insn "avx512f_vextract<shuffletype>32x4_1_maskm"): Ditto.
	(define_insn "<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>"):
	Update `type' attribute, remove explicit `memory' attribute calculation.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215296
parent 7c943bd8
Showing with 77 additions and 0 deletions
gcc/ChangeLog
2014-09-16 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/i386.c
(ix86_expand_vector_extract): Handle V32HI and V64QI modes.
* config/i386/sse.md
(define_mode_iterator VI48F_256): New.
(define_mode_attr extract_type): Ditto.
(define_mode_attr extract_suf): Ditto.
(define_mode_iterator AVX512_VEC): Ditto.
(define_expand
"<extract_type>_vextract<shuffletype><extract_suf>_mask"): Use
AVX512_VEC.
(define_insn "avx512dq_vextract<shuffletype>64x2_1_maskm"): New.
(define_insn
"<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>"):
Ditto.
(define_mode_attr extract_type_2): Ditto.
(define_mode_attr extract_suf_2): Ditto.
(define_mode_iterator AVX512_VEC_2): Ditto.
(define_expand
"<extract_type_2>_vextract<shuffletype><extract_suf_2>_mask"): Use
AVX512_VEC_2 mode iterator.
(define_insn "vec_extract_hi_<mode>_maskm"): Ditto.
(define_expand "avx512vl_vextractf128<mode>"): Ditto.
(define_insn_and_split "vec_extract_lo_<mode>"): Delete.
(define_insn "vec_extract_lo_<mode><mask_name>"): New.
(define_split for V16FI mode): Ditto.
(define_insn_and_split "vec_extract_lo_<mode>"): Delete.
(define_insn "vec_extract_lo_<mode><mask_name>"): New.
(define_split for VI8F_256 mode): Ditto.
(define_insn "vec_extract_hi_<mode><mask_name>"): Add masking.
(define_insn_and_split "vec_extract_lo_<mode>"): Delete.
(define_insn "vec_extract_lo_<mode><mask_name>"): New.
(define_split for VI4F_256 mode): Ditto.
(define_insn "vec_extract_lo_<mode>_maskm"): Ditto.
(define_insn "vec_extract_hi_<mode>_maskm"): Ditto.
(define_insn "vec_extract_hi_<mode><mask_name>"): Add masking.
(define_mode_iterator VEC_EXTRACT_MODE): Add V64QI and V32HI modes.
(define_insn "vcvtph2ps<mask_name>"): Fix pattern condition.
(define_insn "avx512f_vextract<shuffletype>32x4_1_maskm"): Ditto.
(define_insn "<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>"):
Update `type' attribute, remove explicit `memory' attribute calculation.
2014-09-16 Kito Cheng <kito@0xlab.org> 2014-09-16 Kito Cheng <kito@0xlab.org>
* ira.c (ira): Don't initialize ira_spilled_reg_stack_slots and * ira.c (ira): Don't initialize ira_spilled_reg_stack_slots and
gcc/config/i386/i386.c
...@@ -40979,6 +40979,32 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) ...@@ -40979,6 +40979,32 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
} }
break; break;
case V32HImode:
if (TARGET_AVX512BW)
{
tmp = gen_reg_rtx (V16HImode);
if (elt < 16)
emit_insn (gen_vec_extract_lo_v32hi (tmp, vec));
else
emit_insn (gen_vec_extract_hi_v32hi (tmp, vec));
ix86_expand_vector_extract (false, target, tmp, elt & 15);
return;
}
break;
case V64QImode:
if (TARGET_AVX512BW)
{
tmp = gen_reg_rtx (V32QImode);
if (elt < 32)
emit_insn (gen_vec_extract_lo_v64qi (tmp, vec));
else
emit_insn (gen_vec_extract_hi_v64qi (tmp, vec));
ix86_expand_vector_extract (false, target, tmp, elt & 31);
return;
}
break;
case V16SFmode: case V16SFmode:
tmp = gen_reg_rtx (V8SFmode); tmp = gen_reg_rtx (V8SFmode);
if (elt < 8) if (elt < 8)
gcc/config/i386/subst.md
...@@ -57,6 +57,7 @@ ...@@ -57,6 +57,7 @@
(define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)") (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
(define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL") (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
(define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW") (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
(define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
(define_subst_attr "store_mask_constraint" "mask" "vm" "v") (define_subst_attr "store_mask_constraint" "mask" "vm" "v")
(define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand") (define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
(define_subst_attr "mask_prefix" "mask" "vex" "evex") (define_subst_attr "mask_prefix" "mask" "vex" "evex")
......
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