[AArch64] Fix predicate alignment for fixed-length SVE
aarch64_simd_vector_alignment was only giving predicates 16-bit alignment in VLA mode, not VLS mode. I think the problem is latent because we can't yet create an ABI predicate type, but it seemed worth fixing in a standalone patch rather than as part of the main ACLE series. The ACLE patches have tests for this. 2019-08-15 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_simd_vector_alignment): Return 16 for SVE predicates even if they are fixed-length. From-SVN: r274522
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