rtl.h (STORE_FLAG_VALUE): Remove default definition from here.

	* rtl.h (STORE_FLAG_VALUE): Remove default definition from here.
	* defaults.h (STORE_FLAG_VALUE): Move default definition to here.
	* doc/tm.texi (STORE_FLAG_VALUE): Document the default value.

	* config/alpha/alpha.h (STORE_FLAG_VALUE): Remove definition.
	* config/arc/arc.h (STORE_FLAG_VALUE): Likewise.
	* config/arm/arm.h (STORE_FLAG_VALUE): Likewise.
	* config/cris/cris.h (STORE_FLAG_VALUE): Likewise.
	* config/i370/i370.h (STORE_FLAG_VALUE): Likewise.
	* config/i386/i386.h (STORE_FLAG_VALUE): Likewise.
	* config/i960/i960.h (STORE_FLAG_VALUE): Likewise.
	* config/ia64/ia64.h (STORE_FLAG_VALUE): Likewise.
	* config/ip2k/ip2k.h (STORE_FLAG_VALUE): Likewise.
	* config/m32r/m32r.h (STORE_FLAG_VALUE): Likewise.
	* config/mcore/mcore.h (STORE_FLAG_VALUE): Likewise.
	* config/mips/mips.h (STORE_FLAG_VALUE): Likewise.
	* config/mmix/mmix.h (STORE_FLAG_VALUE): Likewise.
	* config/ns32k/ns32k.h (STORE_FLAG_VALUE): Likewise.
	* config/pa/pa.h (STORE_FLAG_VALUE): Likewise.
	* config/pdp11/pdp11.h (STORE_FLAG_VALUE): Likewise.
	* config/sh/sh.h (STORE_FLAG_VALUE): Likewise.
	* config/sparc/sparc.h (STORE_FLAG_VALUE): Likewise.
	* config/v850/v850.h (STORE_FLAG_VALUE): Likewise.
	* config/xtensa/xtensa.h (STORE_FLAG_VALUE): Likewise.

Co-Authored-By: Zack Weinberg <zack@codesourcery.com>

From-SVN: r67957

gcc/ChangeLog

+2003-06-14  Roger Sayle  <roger@eyesopen.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+
+	* rtl.h (STORE_FLAG_VALUE): Remove default definition from here.
+	* defaults.h (STORE_FLAG_VALUE): Move default definition to here.
+	* doc/tm.texi (STORE_FLAG_VALUE): Document the default value.
+
+	* config/alpha/alpha.h (STORE_FLAG_VALUE): Remove definition.
+	* config/arc/arc.h (STORE_FLAG_VALUE): Likewise.
+	* config/arm/arm.h (STORE_FLAG_VALUE): Likewise.
+	* config/cris/cris.h (STORE_FLAG_VALUE): Likewise.
+	* config/i370/i370.h (STORE_FLAG_VALUE): Likewise.
+	* config/i386/i386.h (STORE_FLAG_VALUE): Likewise.
+	* config/i960/i960.h (STORE_FLAG_VALUE): Likewise.
+	* config/ia64/ia64.h (STORE_FLAG_VALUE): Likewise.
+	* config/ip2k/ip2k.h (STORE_FLAG_VALUE): Likewise.
+	* config/m32r/m32r.h (STORE_FLAG_VALUE): Likewise.
+	* config/mcore/mcore.h (STORE_FLAG_VALUE): Likewise.
+	* config/mips/mips.h (STORE_FLAG_VALUE): Likewise.
+	* config/mmix/mmix.h (STORE_FLAG_VALUE): Likewise.
+	* config/ns32k/ns32k.h (STORE_FLAG_VALUE): Likewise.
+	* config/pa/pa.h (STORE_FLAG_VALUE): Likewise.
+	* config/pdp11/pdp11.h (STORE_FLAG_VALUE): Likewise.
+	* config/sh/sh.h (STORE_FLAG_VALUE): Likewise.
+	* config/sparc/sparc.h (STORE_FLAG_VALUE): Likewise.
+	* config/v850/v850.h (STORE_FLAG_VALUE): Likewise.
+	* config/xtensa/xtensa.h (STORE_FLAG_VALUE): Likewise.
+
 2003-06-14  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* opts.sh (POSIXLY_CORRECT): Unset it.

gcc/config/alpha/alpha.h

@@ -1432,11 +1432,6 @@ do {									     \
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* The CIX ctlz and cttz instructions return 64 for zero.  */
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 64, TARGET_CIX)
 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 64, TARGET_CIX)

gcc/config/arc/arc.h

@@ -1295,10 +1295,6 @@ do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-#define STORE_FLAG_VALUE 1
-
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */

gcc/config/arm/arm.h

@@ -2260,8 +2260,6 @@ extern int making_const_table;
     }									\
   while (0)
 
-#define STORE_FLAG_VALUE 1
-
 /* The arm5 clz instruction returns 32.  */
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
 

gcc/config/cris/cris.h

@@ -1679,8 +1679,6 @@ call_ ## FUNC (void)						\
 
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-#define STORE_FLAG_VALUE 1
-
 #define Pmode SImode
 
 #define FUNCTION_MODE QImode

gcc/config/i370/i370.h

@@ -877,10 +877,7 @@ enum reg_class
 
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)	(OUTPREC != 16)
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-/* #define STORE_FLAG_VALUE (-1) */
+/* ??? Investigate defining STORE_FLAG_VALUE to (-1).  */
 
 /* When a prototype says `char' or `short', really pass an `int'.  */
 

gcc/config/i386/i386.h

@@ -2577,11 +2577,6 @@ enum ix86_builtins
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* When a prototype says `char' or `short', really pass an `int'.
    (The 386 can't easily push less than an int.)  */
 

gcc/config/i960/i960.h

@@ -1115,11 +1115,6 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
 
 #define SLOW_BYTE_ACCESS 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* Define this to be nonzero if shift instructions ignore all but the low-order
    few bits.  */
 #define SHIFT_COUNT_TRUNCATED 0

gcc/config/ia64/ia64.h

@@ -2265,9 +2265,7 @@ do {									\
    an integral mode and stored by a store-flag instruction (`sCOND') when the
    condition is true.  */
 
-/* ??? Investigate using -1 instead of 1.  */
-
-#define STORE_FLAG_VALUE 1
+/* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1.  */
 
 /* An alias for the machine mode for pointers.  */
 

gcc/config/ip2k/ip2k.h

@@ -2365,8 +2365,6 @@ extern int ip2k_reorg_merge_qimode;
 
 /* Miscellaneous macros to describe machine specifics. */
 
-#define STORE_FLAG_VALUE	1
-
 #define IS_PSEUDO_P(R)	(REGNO (R) >= FIRST_PSEUDO_REGISTER)
 
 /* Default calculations would cause DWARF address sizes to be 2 bytes,

gcc/config/m32r/m32r.h

@@ -1765,10 +1765,6 @@ extern char m32r_punct_chars[256];
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-#define STORE_FLAG_VALUE 1
-
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */

gcc/config/mcore/mcore.h

@@ -977,10 +977,6 @@ extern const enum reg_class reg_class_from_letter[];
 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-#define STORE_FLAG_VALUE 1
-
 /* Immediate shift counts are truncated by the output routines (or was it
    the assembler?).  Shift counts in a register are truncated by ARM.  Note
    that the native compiler puts too large (> 32) immediate shift counts

gcc/config/mips/mips.h

@@ -3153,11 +3153,6 @@ typedef struct mips_args {
    this as 1, since it avoids making a QI or HI mode register.  */
 #define SLOW_BYTE_ACCESS 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* Define this to be nonzero if shift instructions ignore all but the low-order
    few bits.  */
 #define SHIFT_COUNT_TRUNCATED 1

gcc/config/mmix/mmix.h

@@ -1144,11 +1144,8 @@ typedef struct { int regs; int lib; } CUMULATIVE_ARGS;
 
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We have a choice here too.  */
-#if 0
-/* FIXME:  Revisit, we don't have scc expanders yet.  */
-#define STORE_FLAG_VALUE 1
-#endif
+/* ??? MMIX allows a choice of STORE_FLAG_VALUE.  Revisit later,
+   we don't have scc expanders yet.  */
 
 #define Pmode DImode
 

gcc/config/ns32k/ns32k.h

@@ -1148,11 +1148,6 @@ __transfer_from_trampoline ()		\
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */

gcc/config/pa/pa.h

@@ -1585,11 +1585,6 @@ do { 									\
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* When a prototype says `char' or `short', really pass an `int'.  */
 #define PROMOTE_PROTOTYPES 1
 #define PROMOTE_FUNCTION_RETURN 1

gcc/config/pdp11/pdp11.h

@@ -918,11 +918,6 @@ extern int may_call_alloca;
 #define SELECT_CC_MODE(OP,X,Y)	\
 (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode)
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-/* #define STORE_FLAG_VALUE 1 */
-
 /* Specify the machine mode that pointers have.
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */

gcc/config/sh/sh.h

@@ -2713,11 +2713,6 @@ while (0)
 /* Nonzero if access to memory by bytes is no faster than for words.  */
 #define SLOW_BYTE_ACCESS 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* Immediate shift counts are truncated by the output routines (or was it
    the assembler?).  Shift counts in a register are truncated by SH.  Note
    that the native compiler puts too large (> 32) immediate shift counts

gcc/config/sparc/sparc.h

@@ -2489,11 +2489,6 @@ do {                                                                    \
    and maybe make use of that.  */
 #define SLOW_BYTE_ACCESS 1
 
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
 /* When a prototype says `char' or `short', really pass an `int'.  */
 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
 

gcc/config/v850/v850.h

@@ -1313,8 +1313,6 @@ zbss_section ()								\
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
-#define STORE_FLAG_VALUE 1
-
 #define MULDI3_LIBCALL  "__muldi3"
 #define UCMPDI2_LIBCALL "__ucmpdi2"
 #define CMPDI2_LIBCALL  "__cmpdi2"

gcc/config/xtensa/xtensa.h

@@ -1279,13 +1279,10 @@ typedef struct xtensa_args {
 /* Prefer word-sized loads.  */
 #define SLOW_BYTE_ACCESS 1
 
-/* Xtensa doesn't have any instructions that set integer values based on the
-   results of comparisons, but the simplification code in the combiner also
-   uses this macro.  The value should be either 1 or -1 to enable some
-   optimizations in the combiner; I'm not sure which is better for us.
-   Since we've been using 1 for a while, it should probably stay that way for
-   compatibility.  */
-#define STORE_FLAG_VALUE 1
+/* ??? Xtensa doesn't have any instructions that set integer values
+   based on the results of comparisons, but the simplification code in
+   the combiner also uses STORE_FLAG_VALUE.  The default value (1) is
+   fine for us, but (-1) might be better.  */
 
 /* Shift instructions ignore all but the low-order few bits.  */
 #define SHIFT_COUNT_TRUNCATED 1

gcc/defaults.h

@@ -633,4 +633,9 @@ You Lose!  You must define PREFERRED_DEBUGGING_TYPE!
 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  0
 #endif
 
+/* Provide a default value for STORE_FLAG_VALUE.  */
+#ifndef STORE_FLAG_VALUE
+#define STORE_FLAG_VALUE  1
+#endif
+
 #endif  /* ! GCC_DEFAULTS_H */

gcc/doc/tm.texi

@@ -8797,8 +8797,9 @@ and @code{decscc}, respectively, for the patterns which perform
 @file{rs6000.md} for some examples.  The GNU Superoptizer can be used to
 find such instruction sequences on other machines.
 
-You need not define @code{STORE_FLAG_VALUE} if the machine has no store-flag
-instructions.
+If this macro is not defined, the default value, 1, is used.  You need
+not define @code{STORE_FLAG_VALUE} if the machine has no store-flag
+instructions, or if the value generated by these instructions is 1.
 
 @findex FLOAT_STORE_FLAG_VALUE
 @item FLOAT_STORE_FLAG_VALUE (@var{mode})

gcc/rtl.h

@@ -1952,12 +1952,6 @@ extern rtx output_constant_def		PARAMS ((tree, int));
 /* Called from integrate.c when a deferred constant is inlined.  */
 extern void notice_rtl_inlining_of_deferred_constant PARAMS ((void));
 
-/* Define a default value for STORE_FLAG_VALUE.  */
-
-#ifndef STORE_FLAG_VALUE
-#define STORE_FLAG_VALUE 1
-#endif
-
 /* Nonzero after the second flow pass has completed.
    Set to 1 or 0 by toplev.c  */
 extern int flow2_completed;