arm.c (use_return_insn): Do not use a single return instruction for interrupt…

arm.c (use_return_insn): Do not use a single return instruction for interrupt handelrs which have to...

* config/arm/arm.c (use_return_insn): Do not use a single return instruction
for interrupt handelrs which have to create a stack frame.
(arm_expand_prologue): Do not pre-bias the return address of interrupt handlers
which create a stack frame.

From-SVN: r61698

gcc/ChangeLog

+2003-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* config/arm/arm.c (use_return_insn): Do not use a single return
+	instruction for interrupt handelrs which have to create a stack
+	frame.
+	(arm_expand_prologue): Do not pre-bias the return address of
+	interrupt handlers which create a stack frame.
+
+2003-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* Add sh2e support:
+
+	2002-08-12  Alexandre Oliva  <aoliva@redhat.com>
+
+		* config/sh/sh.c (output_branch) [TARGET_SH2E]: Handle
+		med_cbranches.  Fix logic in short_cbranches.
+
+	2002-04-03  Alexandre Oliva  <aoliva@redhat.com>
+
+		* config/sh/sh.md (delay for cbranch): Don't annul delay
+		slots on SH2e.
+		* config/sh/sh.c (sh_insn_length_adjustment): Add 2 for
+		cbranch with unfilled delay slot on SH2e.
+		(output_branch): Fill with a nop the delay slot of a
+		branch that required a delay slot but didn't get one.
+
+	2002-04-02  Alexandre Oliva  <aoliva@redhat.com>
+
+		* doc/invoke.texi (SH options): Document -m2e.
+		* config/sh/crt1.asm: Add __SH2E__ Next to __SH3E__.
+		* config/sh/lib1funcs.asm: Likewise.
+		* config/sh/sh.c: Replace all uses of TARGET_SH3E with SH2E.
+		* config/sh/sh.h (CPP_SPEC): Define __SH2E__ for -m2e, and
+		not __sh1__.
+		(CONDITIONAL_REGISTER_USAGE): Don't disable FP regs from
+		SH2E up.
+		(SH3E_BIT): Renamed to...
+		(SH_E_BIT): ... this.  Replace all uses.
+		(TARGET_SH2E): Define from SH_E_BIT and TARGET_SH2.
+		Replace all uses of TARGET_SH3E with TARGET_SH2E.
+		(TARGET_SWITCHES): Added 2e.
+		(OVERRIDE_OPTIONS): Set sh_cpu for SH2E.
+		(processor_type): Added PROCESSOR_SH2E.
+		* config/sh/sh.md: Replace all uses of TARGET_SH3E with
+		TARGET_SH2E, except in sqrtsf2_i.
+		(attribute cpu): Added sh2e.
+		* config/sh/t-sh (MULTILIB_OPTIONS): Replace m3e with m2e.
+		(MULTILIB_MATCHES): Use m2e multilib for m3e.
+		* config.gcc: Add sh2e target support.
+
 2003-01-24  Phil Edwards  <pme@gcc.gnu.org>
 
 	Rename -W to -Wextra.

gcc/config/arm/arm.c

@@ -938,6 +938,10 @@ use_return_insn (iscond)
      consideration.  */
   if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
     return 0;
+
+  /* So do interrupt functions that use the frame pointer.  */
+  if (IS_INTERRUPT (func_type) && frame_pointer_needed)
+    return 0;
   
   /* As do variadic functions.  */
   if (current_function_pretend_args_size
@@ -7092,7 +7096,7 @@ output_move_double (operands)
 		    {
 		      if (GET_CODE (otherops[2]) == CONST_INT)
 			{
-			  switch (INTVAL (otherops[2]))
+			  switch ((int) INTVAL (otherops[2]))
 			    {
 			    case -8:
 			      output_asm_insn ("ldm%?db\t%1, %M0", otherops);
@@ -7168,7 +7172,7 @@ output_move_double (operands)
 	case PLUS:
 	  if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
 	    {
-	      switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
+	      switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
 		{
 		case -8:
 		  output_asm_insn ("stm%?db\t%m0, %M1", operands);
@@ -8813,18 +8817,19 @@ arm_expand_prologue ()
       RTX_FRAME_RELATED_P (insn) = 1;
     }
 
-  /* If this is an interrupt service routine, and the link register is
-     going to be pushed, subtracting four now will mean that the
-     function return can be done with a single instruction.  */
+  /* If this is an interrupt service routine, and the link register
+     is going to be pushed, and we are not creating a stack frame,
+     (which would involve an extra push of IP and a pop in the epilogue)
+     subtracting four from LR now will mean that the function return
+     can be done with a single instruction.  */
   if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
-      && (live_regs_mask & (1 << LR_REGNUM)) != 0)
-    {
-      emit_insn (gen_rtx_SET (SImode, 
-			      gen_rtx_REG (SImode, LR_REGNUM),
-			      gen_rtx_PLUS (SImode,
-				    gen_rtx_REG (SImode, LR_REGNUM),
-				    GEN_INT (-4))));
-    }
+      && (live_regs_mask & (1 << LR_REGNUM)) != 0
+      && ! frame_pointer_needed)
+    emit_insn (gen_rtx_SET (SImode, 
+			    gen_rtx_REG (SImode, LR_REGNUM),
+			    gen_rtx_PLUS (SImode,
+					  gen_rtx_REG (SImode, LR_REGNUM),
+					  GEN_INT (-4))));
 
   if (live_regs_mask)
     {