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riscv-gcc-1
Commit 057f9d20 by Julia Koval Committed by Julia Koval
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Fix documentation for CLWB ISA. 

gcc/
	* doc/invoke.texi (Skylake Server): Add CLWB.
	Cannonlake): Remove CLWB.

From-SVN: r258587
parent 7b9be700
Showing with 7 additions and 2 deletions
gcc/ChangeLog
2018-03-16 Julia Koval <julia.koval@intel.com>
* doc/invoke.texi (Skylake Server): Add CLWB.
Cannonlake): Remove CLWB.
2018-03-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/84841
......
gcc/doc/invoke.texi
......@@ -26550,14 +26550,14 @@ AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
@item cannonlake
Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
AVX512IFMA, SHA and UMIP instruction set support.
@item icelake-client
Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
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