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riscv-gcc-1
Commit 048d0d36 by Maxim Kuvyrkov Committed by Maxim Kuvyrkov
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ia64.c (stops_p): Added explicit initialization. 

2006-03-16  Maxim Kuvyrkov <mkuvyrkov@ispras.ru>

        * config/ia64/ia64.c (stops_p): Added explicit initialization.
        (ia64_first_cycle_multipass_dfa_lookahead_guard_spec,
        ia64_h_i_d_extended, ia64_set_sched_flags, ia64_speculate_insn,
        ia64_needs_block_p, ia64_gen_check, ia64_sched_init_global,
	ia64_sched_finish_global): New static functions to implement
	hooks from gcc_target.sched.
	(spec_check_no, max_uid, pending_data_specs): New static variables.
        (ia64_mode_to_int, ia64_gen_spec_insn, ia64_spec_check_p,
	ia64_spec_check_src_p): New static functions.
        (ia64_adjust_cost): Renamed to ia64_adjust_cost_2.
        (TARGET_SCHED_ADJUST_COST): Removed.
        (TARGET_SCHED_ADJUST_COST_2, TARGET_SCHED_INIT_GLOBAL,
	TARGET_SCHED_FINISH_GLOBAL, TARGET_SCHED_H_I_D_EXTENDED,
	TARGET_SCHED_SPECULATE_INSN, TARGET_SCHED_NEEDS_BLOCK_P,
	TARGET_SCHED_GEN_CHECK,
	TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC,
        TARGET_SCHED_SET_SCHED_FLAGS): New macros.
        (update_set_flags, group_barrier_needed, set_src_needs_barrier):
	Fixed to handle speculation checks.
        (rtx_needs_barrier): Fixed to handle speculative loads and
        their checks.
        (ia64_variable_issue): Added code to count speculative loads and their
        checks.
        (ia64_first_cycle_multipass_dfa_lookahead_guard): Fixed to handle
        speculative loads.
        (enum SPEC_MODES, enum SPEC_GEN_LD_MAP, SPEC_GEN_CHECK_OFFSET):
        New enumerations.
        (SPEC_GEN_EXTEND_OFFSET, SPEC_N, SPEC_GEN_CHECK_MUTATION_OFFSET):
        New constants.
        (ia64_ld_address_bypass_p): Fixed to handle speculative loads.
	(ia64_reorg): Reset stops_p to NULL after it is freed.
        * config/ia64/ia64.md (UNSPEC_LDA, UNSPEC_LDS, UNSPEC_LDSA,
	UNSPEC_LDCCLR, UNSPEC_CHKACLR, UNSPEC_CHKS): New constants.
        (itanium_class): chk_s renamed to chk_s_i.  New constants: chk_s_f,
        chk_a.
        (data_speculative, control_speculative, check_load): New attributes.
        (mov<mode>_advanced, mov<mode>_speculative,
        mov<mode>_speculative_advanced, zero_extend<mode>di2_advanced,
        zero_extend<mode>di2_speculative,
        zero_extend<mode>di2_speculative_advanced): New patterns for
        data and control speculative loads.
        (mov<mode>_clr, zero_extend<mode>di2_clr): New patterns for
        check loads.
        (advanced_load_check_clr_<mode>, speculation_check_<mode>):
        New pattern for data and control speculation checks.
	(MODE, MODE_FOR_EXTEND, output_a, output_s, output_sa, output_c_clr,
	ld_reg_constr, ldc_reg_constr, chk_reg_constr, mem_constr,
	reg_pred_prefix, ld_class, chka_class, chks_class, attr_yes):
	Auxiliary definitions for the patterns.
        * config/ia64/itanium1.md (1_fldc, 1_fldpc, 1_ldc, 1_chk_s_f, 1_chk_a,
        1b_fldc, 1b_fldpc, 1b_ldc, 1b_chk_s_f, 1b_chk_a): New resource
        constraints.
	(1_fld, 1_fldp, 1_ld, 1b_fld, 1b_fldp, 1b_ld): Add a condition
        for speculation.
        (1_chk_s, 1b_chk_s): Renamed to 1_chk_s_i, 1b_chk_s_i.
        * config/ia64/itanium2.md (2_flda, 2_fldc, 2_fldpc, 2_ldc, 2_chk_s_f,
	2_chk_a, 2b_flda, 2b_fldc, 2b_fldpc, 2b_ldc, 2b_chk_s_f, 2b_chk_a):
	New resource constraints.
	(2_fld, 2_fldp, 2_ld, 2b_fld, 2b_fldp, 2b_ld): Add a condition
        for speculation.
        (2_chk_s, 2b_chk_s): Renamed to 2_chk_s_i, 2b_chk_s_i.
        * config/ia64/ia64.opt (msched-br-data-spec, msched-ar-data-spec,
        msched-control-spec, msched-br-in-data-spec, msched-ar-in-data-spec,
        msched-in-control-spec, msched-ldc, msched-control-ldc,
        msched-spec-verbose, msched-prefer-non-data-spec-insns,
        msched-prefer-non-control-spec-insns,
	msched-count-spec-in-critical-path): New flags to tune speculative
	scheduling.
	* doc/invoke.texi (msched-br-data-spec, msched-ar-data-spec,
        msched-control-spec, msched-br-in-data-spec, msched-ar-in-data-spec,
        msched-in-control-spec, msched-ldc, msched-control-ldc,
        msched-spec-verbose, msched-prefer-non-data-spec-insns,
        msched-prefer-non-control-spec-insns,
	msched-count-spec-in-critical-path): Document new flags.

From-SVN: r112129
parent 496d7bb0
Showing with 640 additions and 54 deletions
gcc/ChangeLog
2006-03-16 Maxim Kuvyrkov <mkuvyrkov@ispras.ru> 2006-03-16 Maxim Kuvyrkov <mkuvyrkov@ispras.ru>
* config/ia64/ia64.c (stops_p): Added explicit initialization.
(ia64_first_cycle_multipass_dfa_lookahead_guard_spec,
ia64_h_i_d_extended, ia64_set_sched_flags, ia64_speculate_insn,
ia64_needs_block_p, ia64_gen_check, ia64_sched_init_global,
ia64_sched_finish_global): New static functions to implement
hooks from gcc_target.sched.
(spec_check_no, max_uid, pending_data_specs): New static variables.
(ia64_mode_to_int, ia64_gen_spec_insn, ia64_spec_check_p,
ia64_spec_check_src_p): New static functions.
(ia64_adjust_cost): Renamed to ia64_adjust_cost_2.
(TARGET_SCHED_ADJUST_COST): Removed.
(TARGET_SCHED_ADJUST_COST_2, TARGET_SCHED_INIT_GLOBAL,
TARGET_SCHED_FINISH_GLOBAL, TARGET_SCHED_H_I_D_EXTENDED,
TARGET_SCHED_SPECULATE_INSN, TARGET_SCHED_NEEDS_BLOCK_P,
TARGET_SCHED_GEN_CHECK,
TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC,
TARGET_SCHED_SET_SCHED_FLAGS): New macros.
(update_set_flags, group_barrier_needed, set_src_needs_barrier):
Fixed to handle speculation checks.
(rtx_needs_barrier): Fixed to handle speculative loads and
their checks.
(ia64_variable_issue): Added code to count speculative loads and their
checks.
(ia64_first_cycle_multipass_dfa_lookahead_guard): Fixed to handle
speculative loads.
(enum SPEC_MODES, enum SPEC_GEN_LD_MAP, SPEC_GEN_CHECK_OFFSET):
New enumerations.
(SPEC_GEN_EXTEND_OFFSET, SPEC_N, SPEC_GEN_CHECK_MUTATION_OFFSET):
New constants.
(ia64_ld_address_bypass_p): Fixed to handle speculative loads.
(ia64_reorg): Reset stops_p to NULL after it is freed.
* config/ia64/ia64.md (UNSPEC_LDA, UNSPEC_LDS, UNSPEC_LDSA,
UNSPEC_LDCCLR, UNSPEC_CHKACLR, UNSPEC_CHKS): New constants.
(itanium_class): chk_s renamed to chk_s_i. New constants: chk_s_f,
chk_a.
(data_speculative, control_speculative, check_load): New attributes.
(mov<mode>_advanced, mov<mode>_speculative,
mov<mode>_speculative_advanced, zero_extend<mode>di2_advanced,
zero_extend<mode>di2_speculative,
zero_extend<mode>di2_speculative_advanced): New patterns for
data and control speculative loads.
(mov<mode>_clr, zero_extend<mode>di2_clr): New patterns for
check loads.
(advanced_load_check_clr_<mode>, speculation_check_<mode>):
New pattern for data and control speculation checks.
(MODE, MODE_FOR_EXTEND, output_a, output_s, output_sa, output_c_clr,
ld_reg_constr, ldc_reg_constr, chk_reg_constr, mem_constr,
reg_pred_prefix, ld_class, chka_class, chks_class, attr_yes):
Auxiliary definitions for the patterns.
* config/ia64/itanium1.md (1_fldc, 1_fldpc, 1_ldc, 1_chk_s_f, 1_chk_a,
1b_fldc, 1b_fldpc, 1b_ldc, 1b_chk_s_f, 1b_chk_a): New resource
constraints.
(1_fld, 1_fldp, 1_ld, 1b_fld, 1b_fldp, 1b_ld): Add a condition
for speculation.
(1_chk_s, 1b_chk_s): Renamed to 1_chk_s_i, 1b_chk_s_i.
* config/ia64/itanium2.md (2_flda, 2_fldc, 2_fldpc, 2_ldc, 2_chk_s_f,
2_chk_a, 2b_flda, 2b_fldc, 2b_fldpc, 2b_ldc, 2b_chk_s_f, 2b_chk_a):
New resource constraints.
(2_fld, 2_fldp, 2_ld, 2b_fld, 2b_fldp, 2b_ld): Add a condition
for speculation.
(2_chk_s, 2b_chk_s): Renamed to 2_chk_s_i, 2b_chk_s_i.
* config/ia64/ia64.opt (msched-br-data-spec, msched-ar-data-spec,
msched-control-spec, msched-br-in-data-spec, msched-ar-in-data-spec,
msched-in-control-spec, msched-ldc, msched-control-ldc,
msched-spec-verbose, msched-prefer-non-data-spec-insns,
msched-prefer-non-control-spec-insns,
msched-count-spec-in-critical-path): New flags to tune speculative
scheduling.
* doc/invoke.texi (msched-br-data-spec, msched-ar-data-spec,
msched-control-spec, msched-br-in-data-spec, msched-ar-in-data-spec,
msched-in-control-spec, msched-ldc, msched-control-ldc,
msched-spec-verbose, msched-prefer-non-data-spec-insns,
msched-prefer-non-control-spec-insns,
msched-count-spec-in-critical-path): Document new flags.
2006-03-16 Maxim Kuvyrkov <mkuvyrkov@ispras.ru>
* target.h (struct spec_info_def): New opaque declaration. * target.h (struct spec_info_def): New opaque declaration.
(struct gcc_target.sched): New fields: adjust_cost_2, h_i_d_extended, (struct gcc_target.sched): New fields: adjust_cost_2, h_i_d_extended,
speculate_insn, needs_block_p, gen_check, speculate_insn, needs_block_p, gen_check,
......
gcc/config/ia64/ia64.md
...@@ -81,6 +81,12 @@ ...@@ -81,6 +81,12 @@
(UNSPEC_SHRP 29) (UNSPEC_SHRP 29)
(UNSPEC_COPYSIGN 30) (UNSPEC_COPYSIGN 30)
(UNSPEC_VECT_EXTR 31) (UNSPEC_VECT_EXTR 31)
(UNSPEC_LDA 40)
(UNSPEC_LDS 41)
(UNSPEC_LDSA 42)
(UNSPEC_LDCCLR 43)
(UNSPEC_CHKACLR 45)
(UNSPEC_CHKS 47)
]) ])
(define_constants (define_constants
...@@ -124,18 +130,19 @@ ...@@ -124,18 +130,19 @@
(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
ld,chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
(const_string "unknown")) (const_string "unknown"))
;; chk_s has an I and an M form; use type A for convenience. ;; chk_s_i has an I and an M form; use type A for convenience.
(define_attr "type" "unknown,A,I,M,F,B,L,X,S" (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
(cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
(eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
(eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
(eq_attr "itanium_class" "lfetch") (const_string "M") (eq_attr "itanium_class" "lfetch") (const_string "M")
(eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua") (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M")
(eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua")
(const_string "A") (const_string "A")
(eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
(eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
...@@ -170,6 +177,12 @@ ...@@ -170,6 +177,12 @@
;; when we have full intrinsics support. ;; when we have full intrinsics support.
(define_attr "first_insn" "no,yes" (const_string "no")) (define_attr "first_insn" "no,yes" (const_string "no"))
(define_attr "data_speculative" "no,yes" (const_string "no"))
(define_attr "control_speculative" "no,yes" (const_string "no"))
(define_attr "check_load" "no,yes" (const_string "no"))
;; DFA descriptions of ia64 processors used for insn scheduling and ;; DFA descriptions of ia64 processors used for insn scheduling and
;; bundling. ;; bundling.
...@@ -372,6 +385,191 @@ ...@@ -372,6 +385,191 @@
} }
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
(define_mode_macro MODE [BI QI HI SI DI SF DF XF TI])
(define_mode_macro MODE_FOR_EXTEND [QI HI SI])
(define_mode_attr output_a [
(BI "ld1.a %0 = %1%P1")
(QI "ld1.a %0 = %1%P1")
(HI "ld2.a %0 = %1%P1")
(SI "ld4.a %0 = %1%P1")
(DI
"@
ld8.a %0 = %1%P1
ldf8.a %0 = %1%P1")
(SF
"@
ldfs.a %0 = %1%P1
ld4.a %0 = %1%P1")
(DF
"@
ldfd.a %0 = %1%P1
ld8.a %0 = %1%P1")
(XF "ldfe.a %0 = %1%P1")
(TI "ldfp8.a %X0 = %1%P1")])
(define_mode_attr output_s [
(BI "ld1.s %0 = %1%P1")
(QI "ld1.s %0 = %1%P1")
(HI "ld2.s %0 = %1%P1")
(SI "ld4.s %0 = %1%P1")
(DI
"@
ld8.s %0 = %1%P1
ldf8.s %0 = %1%P1")
(SF
"@
ldfs.s %0 = %1%P1
ld4.s %0 = %1%P1")
(DF
"@
ldfd.s %0 = %1%P1
ld8.s %0 = %1%P1")
(XF "ldfe.s %0 = %1%P1")
(TI "ldfp8.s %X0 = %1%P1")])
(define_mode_attr output_sa [
(BI "ld1.sa %0 = %1%P1")
(QI "ld1.sa %0 = %1%P1")
(HI "ld2.sa %0 = %1%P1")
(SI "ld4.sa %0 = %1%P1")
(DI
"@
ld8.sa %0 = %1%P1
ldf8.sa %0 = %1%P1")
(SF
"@
ldfs.sa %0 = %1%P1
ld4.sa %0 = %1%P1")
(DF
"@
ldfd.sa %0 = %1%P1
ld8.sa %0 = %1%P1")
(XF "ldfe.sa %0 = %1%P1")
(TI "ldfp8.sa %X0 = %1%P1")])
(define_mode_attr output_c_clr [
(BI "ld1.c.clr%O1 %0 = %1%P1")
(QI "ld1.c.clr%O1 %0 = %1%P1")
(HI "ld2.c.clr%O1 %0 = %1%P1")
(SI "ld4.c.clr%O1 %0 = %1%P1")
(DI
"@
ld8.c.clr%O1 %0 = %1%P1
ldf8.c.clr %0 = %1%P1")
(SF
"@
ldfs.c.clr %0 = %1%P1
ld4.c.clr%O1 %0 = %1%P1")
(DF
"@
ldfd.c.clr %0 = %1%P1
ld8.c.clr%O1 %0 = %1%P1")
(XF "ldfe.c.clr %0 = %1%P1")
(TI "ldfp8.c.clr %X0 = %1%P1")])
(define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
(define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
(define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
(define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")])
(define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")])
(define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")])
(define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")])
(define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")])
(define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")])
(define_insn "mov<mode>_advanced"
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
(unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))]
"ia64_move_ok (operands[0], operands[1])"
"<output_a>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "data_speculative" "<attr_yes>")])
(define_insn "zero_extend<mode>di2_advanced"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))]
""
"<output_a>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "data_speculative" "<attr_yes>")])
(define_insn "mov<mode>_speculative"
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
(unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))]
"ia64_move_ok (operands[0], operands[1])"
"<output_s>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "control_speculative" "<attr_yes>")])
(define_insn "zero_extend<mode>di2_speculative"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))]
""
"<output_s>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "control_speculative" "<attr_yes>")])
(define_insn "mov<mode>_speculative_advanced"
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
(unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))]
"ia64_move_ok (operands[0], operands[1])"
"<output_sa>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "data_speculative" "<attr_yes>")
(set_attr "control_speculative" "<attr_yes>")])
(define_insn "zero_extend<mode>di2_speculative_advanced"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
""
"<output_sa>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "data_speculative" "<attr_yes>")
(set_attr "control_speculative" "<attr_yes>")])
(define_insn "mov<mode>_clr"
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
(if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
(match_operand:MODE 1 "memory_operand" "<mem_constr>")
(match_dup 0)))]
"ia64_move_ok (operands[0], operands[1])"
"<output_c_clr>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "check_load" "<attr_yes>")])
(define_insn "zero_extend<mode>di2_clr"
[(set (match_operand:DI 0 "gr_register_operand" "+r")
(if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
(zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
(match_dup 0)))]
""
"<output_c_clr>"
[(set_attr "itanium_class" "<ld_class>")
(set_attr "check_load" "<attr_yes>")])
(define_insn "advanced_load_check_clr_<mode>"
[(set (pc)
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
(pc)
(label_ref (match_operand 1 "" ""))))]
""
"chk.a.clr %0, %l1"
[(set_attr "itanium_class" "<chka_class>")])
(define_insn "speculation_check_<mode>"
[(set (pc)
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
(pc)
(label_ref (match_operand 1 "" ""))))]
""
"chk.s %0, %l1"
[(set_attr "itanium_class" "<chks_class>")])
(define_split (define_split
[(set (match_operand 0 "register_operand" "") [(set (match_operand 0 "register_operand" "")
(match_operand 1 "symbolic_operand" ""))] (match_operand 1 "symbolic_operand" ""))]
...@@ -6114,7 +6312,7 @@ ...@@ -6114,7 +6312,7 @@
[(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
"" ""
"break %0" "break %0"
[(set_attr "itanium_class" "chk_s")]) [(set_attr "itanium_class" "chk_s_i")])
(define_expand "conditional_trap" (define_expand "conditional_trap"
[(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
...@@ -6130,7 +6328,7 @@ ...@@ -6130,7 +6328,7 @@
(match_operand 2 "const_int_operand" ""))] (match_operand 2 "const_int_operand" ""))]
"" ""
"(%J0) break %2" "(%J0) break %2"
[(set_attr "itanium_class" "chk_s") [(set_attr "itanium_class" "chk_s_i")
(set_attr "predicable" "no")]) (set_attr "predicable" "no")])
(define_insn "break_f" (define_insn "break_f"
......
gcc/config/ia64/ia64.opt
...@@ -96,3 +96,50 @@ mtune= ...@@ -96,3 +96,50 @@ mtune=
Target RejectNegative Joined Target RejectNegative Joined
Schedule code for given CPU Schedule code for given CPU
msched-br-data-spec
Target Report Var(mflag_sched_br_data_spec) Init(0)
Use data speculation before reload
msched-ar-data-spec
Target Report Var(mflag_sched_ar_data_spec) Init(1)
Use data speculation after reload
msched-control-spec
Target Report Var(mflag_sched_control_spec) Init(0)
Use control speculation
msched-br-in-data-spec
Target Report Var(mflag_sched_br_in_data_spec) Init(1)
Use in block data speculation before reload
msched-ar-in-data-spec
Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
Use in block data speculation after reload
msched-in-control-spec
Target Report Var(mflag_sched_in_control_spec) Init(1)
Use in block control speculation
msched-ldc
Target Report Var(mflag_sched_ldc) Init(1)
Use simple data speculation check
msched-control-ldc
Target Report Var(mflag_control_ldc) Init(0)
Use simple data speculation check for control speculation
msched-spec-verbose
Common Report Var(mflag_sched_spec_verbose) Init(0)
Print information about speculative motions.
msched-prefer-non-data-spec-insns
Common Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
If set, data speculative instructions will be choosen for schedule only if there are no other choices at the moment
msched-prefer-non-control-spec-insns
Common Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
If set, control speculative instructions will be choosen for schedule only if there are no other choices at the moment
msched-count-spec-in-critical-path
Common Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
Count speculative dependencies while calculating priority of instructions
gcc/config/ia64/itanium1.md
...@@ -525,14 +525,29 @@ ...@@ -525,14 +525,29 @@
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fcvtfx")) (eq_attr "itanium_class" "fcvtfx"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F") (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fld" 9 (define_insn_reservation "1_fld" 9
(and (and (eq_attr "cpu" "itanium") (and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fld")) (eq_attr "itanium_class" "fld"))
(eq_attr "check_load" "no"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M") (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fldc" 0
(and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fld"))
(eq_attr "check_load" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fldp" 9 (define_insn_reservation "1_fldp" 9
(and (and (eq_attr "cpu" "itanium") (and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fldp")) (eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "no"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fldpc" 0
(and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M") (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fmac" 5 (define_insn_reservation "1_fmac" 5
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fmac")) (eq_attr "itanium_class" "fmac"))
...@@ -604,8 +619,14 @@ ...@@ -604,8 +619,14 @@
(eq (symbol_ref "bundling_p") (const_int 0))) (eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1") "1_I+1_not_ui1")
(define_insn_reservation "1_ld" 2 (define_insn_reservation "1_ld" 2
(and (and (eq_attr "cpu" "itanium") (and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "ld")) (eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "no"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_ldc" 0
(and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M") (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_long_i" 1 (define_insn_reservation "1_long_i" 1
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
...@@ -696,10 +717,19 @@ ...@@ -696,10 +717,19 @@
(eq_attr "itanium_class" "xtd")) (eq_attr "itanium_class" "xtd"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I") (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
(define_insn_reservation "1_chk_s" 0 (define_insn_reservation "1_chk_s_i" 0
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "chk_s")) (eq_attr "itanium_class" "chk_s_i"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A") (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_chk_s_f" 0
(and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "chk_s_f"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_chk_a" 0
(and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "chk_a"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_lfetch" 0 (define_insn_reservation "1_lfetch" 0
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "lfetch")) (eq_attr "itanium_class" "lfetch"))
...@@ -943,15 +973,15 @@ ...@@ -943,15 +973,15 @@
(define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p") (define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p")
(define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p") (define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p")
(define_bypass 3 "1_ld" "1_mmmul,1_mmshf") (define_bypass 3 "1_ld,1_ldc" "1_mmmul,1_mmshf")
(define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p") (define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p")
(define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p") (define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p")
;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4, ;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4,
;; but HP engineers say any non-MM operation. ;; but HP engineers say any non-MM operation.
(define_bypass 4 "1_mmmul,1_mmshf,1_mmalua" (define_bypass 4 "1_mmmul,1_mmshf,1_mmalua"
"1_br,1_fcmp,1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ "1_br,1_fcmp,1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_chk_s,\ 1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,1_chk_s_i,1_chk_s_f,1_chk_a,\
1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\ 1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\
1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd") 1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd")
...@@ -965,15 +995,15 @@ ...@@ -965,15 +995,15 @@
(define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf") (define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf")
;; We don't use here fcmp because scall may be predicated. ;; We don't use here fcmp because scall may be predicated.
(define_bypass 0 "1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ (define_bypass 0 "1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\ 1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\
1_ld,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_toar_m,\ 1_ld,1_ldc,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,\
1_tofr,1_xmpy,1_xtd" "1_scall") 1_toar_m,1_tofr,1_xmpy,1_xtd" "1_scall")
(define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\ (define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\
1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\ 1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\
1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,\ 1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,\
1_chk_s,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\ 1_chk_s_i,1_chk_s_f,1_chk_a,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\ 1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\
1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\ 1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\
1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch" 1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch"
...@@ -1407,14 +1437,29 @@ ...@@ -1407,14 +1437,29 @@
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fcvtfx")) (eq_attr "itanium_class" "fcvtfx"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_fld" 9 (define_insn_reservation "1b_fld" 9
(and (and (eq_attr "cpu" "itanium") (and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fld")) (eq_attr "itanium_class" "fld"))
(eq_attr "check_load" "no"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_fldc" 0
(and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fld"))
(eq_attr "check_load" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_fldp" 9 (define_insn_reservation "1b_fldp" 9
(and (and (eq_attr "cpu" "itanium") (and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fldp")) (eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "no"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_fldpc" 0
(and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_fmac" 5 (define_insn_reservation "1b_fmac" 5
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "fmac")) (eq_attr "itanium_class" "fmac"))
...@@ -1480,10 +1525,18 @@ ...@@ -1480,10 +1525,18 @@
(eq_attr "itanium_class" "ishf")) (eq_attr "itanium_class" "ishf"))
(ne (symbol_ref "bundling_p") (const_int 0))) (ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1") "1b_I+1b_not_ui1")
(define_insn_reservation "1b_ld" 2 (define_insn_reservation "1b_ld" 2
(and (and (eq_attr "cpu" "itanium") (and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "ld")) (eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "no"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_ldc" 0
(and (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_long_i" 1 (define_insn_reservation "1b_long_i" 1
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "long_i")) (eq_attr "itanium_class" "long_i"))
...@@ -1566,10 +1619,20 @@ ...@@ -1566,10 +1619,20 @@
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "xtd")) (eq_attr "itanium_class" "xtd"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_chk_s" 0
(define_insn_reservation "1b_chk_s_i" 0
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "chk_s")) (eq_attr "itanium_class" "chk_s_i"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_chk_s_f" 0
(and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "chk_s_f"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_chk_a" 0
(and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "chk_a"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_lfetch" 0 (define_insn_reservation "1b_lfetch" 0
(and (and (eq_attr "cpu" "itanium") (and (and (eq_attr "cpu" "itanium")
(eq_attr "itanium_class" "lfetch")) (eq_attr "itanium_class" "lfetch"))
......
gcc/config/ia64/itanium2.md
...@@ -731,14 +731,38 @@ ...@@ -731,14 +731,38 @@
(eq_attr "itanium_class" "fcvtfx")) (eq_attr "itanium_class" "fcvtfx"))
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F") (eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
(define_insn_reservation "2_fld" 6 (define_insn_reservation "2_fld" 6
(and (and (eq_attr "cpu" "itanium2") (and (and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fld")) (eq_attr "itanium_class" "fld"))
(eq (symbol_ref "bundling_p") (const_int 0))) "2_M") (eq_attr "data_speculative" "no"))
(eq_attr "check_load" "no"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M")
(define_insn_reservation "2_flda" 6
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fld"))
(eq_attr "data_speculative" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01")
(define_insn_reservation "2_fldc" 0
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fld"))
(eq_attr "check_load" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01")
(define_insn_reservation "2_fldp" 6 (define_insn_reservation "2_fldp" 6
(and (and (eq_attr "cpu" "itanium2") (and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fldp")) (eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "no"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01")
(define_insn_reservation "2_fldpc" 0
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0))) (eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01") "2_M_only_um01")
(define_insn_reservation "2_fmac" 4 (define_insn_reservation "2_fmac" 4
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fmac")) (eq_attr "itanium_class" "fmac"))
...@@ -801,11 +825,19 @@ ...@@ -801,11 +825,19 @@
(eq_attr "itanium_class" "ishf")) (eq_attr "itanium_class" "ishf"))
(eq (symbol_ref "bundling_p") (const_int 0))) (eq (symbol_ref "bundling_p") (const_int 0)))
"2_I+2_only_ui0") "2_I+2_only_ui0")
(define_insn_reservation "2_ld" 1 (define_insn_reservation "2_ld" 1
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "no"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01")
(define_insn_reservation "2_ldc" 0
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "ld")) (eq_attr "check_load" "yes"))
(eq (symbol_ref "bundling_p") (const_int 0))) (eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01") "2_M_only_um01")
(define_insn_reservation "2_long_i" 1 (define_insn_reservation "2_long_i" 1
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "long_i")) (eq_attr "itanium_class" "long_i"))
...@@ -909,11 +941,22 @@ ...@@ -909,11 +941,22 @@
(eq_attr "itanium_class" "xtd")) (eq_attr "itanium_class" "xtd"))
(eq (symbol_ref "bundling_p") (const_int 0))) "2_I") (eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
(define_insn_reservation "2_chk_s" 0 (define_insn_reservation "2_chk_s_i" 0
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "chk_s")) (eq_attr "itanium_class" "chk_s_i"))
(eq (symbol_ref "bundling_p") (const_int 0))) (eq (symbol_ref "bundling_p") (const_int 0)))
"2_I|2_M_only_um23") "2_I|2_M_only_um23")
(define_insn_reservation "2_chk_s_f" 0
(and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "chk_s_f"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um23")
(define_insn_reservation "2_chk_a" 0
(and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "chk_a"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"2_M_only_um01")
(define_insn_reservation "2_lfetch" 0 (define_insn_reservation "2_lfetch" 0
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "lfetch")) (eq_attr "itanium_class" "lfetch"))
...@@ -1025,23 +1068,23 @@ ...@@ -1025,23 +1068,23 @@
(define_bypass 0 "2_tbit" "2_br,2_scall") (define_bypass 0 "2_tbit" "2_br,2_scall")
(define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p") (define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p")
(define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p") (define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p")
(define_bypass 2 "2_ld" "2_mmalua,2_mmmul,2_mmshf") (define_bypass 2 "2_ld,2_ldc" "2_mmalua,2_mmmul,2_mmshf")
(define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf") (define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf")
(define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf") (define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf")
(define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld") (define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld,2_ldc")
(define_bypass 6 "2_tofr" "2_frfr,2_stf") (define_bypass 6 "2_tofr" "2_frfr,2_stf")
(define_bypass 7 "2_fmac" "2_frfr,2_stf") (define_bypass 7 "2_fmac" "2_frfr,2_stf")
;; We don't use here fcmp because scall may be predicated. ;; We don't use here fcmp because scall may be predicated.
(define_bypass 0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ (define_bypass 0 "2_fcvtfx,2_fld,2_flda,2_fldc,2_fmac,2_fmisc,2_frar_i,2_frar_m,\
2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\ 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_ldc,2_long_i,\
2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\ 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\
2_xmpy,2_xtd" 2_xmpy,2_xtd"
"2_scall") "2_scall")
(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\ (define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,2_flda,2_fldc,\
2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\ 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\
2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,2_long_i,\ 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_ldc,2_chk_s_i,2_chk_s_f,2_chk_a,2_long_i,\
2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\ 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\ 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\
2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\ 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\
...@@ -1543,14 +1586,38 @@ ...@@ -1543,14 +1586,38 @@
(eq_attr "itanium_class" "fcvtfx")) (eq_attr "itanium_class" "fcvtfx"))
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
(define_insn_reservation "2b_fld" 6 (define_insn_reservation "2b_fld" 6
(and (and (eq_attr "cpu" "itanium2") (and (and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fld")) (eq_attr "itanium_class" "fld"))
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_M") (eq_attr "data_speculative" "no"))
(eq_attr "check_load" "no"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M")
(define_insn_reservation "2b_flda" 6
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fld"))
(eq_attr "data_speculative" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01")
(define_insn_reservation "2b_fldc" 0
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fld"))
(eq_attr "check_load" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01")
(define_insn_reservation "2b_fldp" 6 (define_insn_reservation "2b_fldp" 6
(and (and (eq_attr "cpu" "itanium2") (and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fldp")) (eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "no"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01")
(define_insn_reservation "2b_fldpc" 0
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fldp"))
(eq_attr "check_load" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0))) (ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01") "2b_M_only_um01")
(define_insn_reservation "2b_fmac" 4 (define_insn_reservation "2b_fmac" 4
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "fmac")) (eq_attr "itanium_class" "fmac"))
...@@ -1611,11 +1678,20 @@ ...@@ -1611,11 +1678,20 @@
(eq_attr "itanium_class" "ishf")) (eq_attr "itanium_class" "ishf"))
(ne (symbol_ref "bundling_p") (const_int 0))) (ne (symbol_ref "bundling_p") (const_int 0)))
"2b_I+2b_only_ui0") "2b_I+2b_only_ui0")
(define_insn_reservation "2b_ld" 1 (define_insn_reservation "2b_ld" 1
(and (and (eq_attr "cpu" "itanium2") (and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "ld")) (eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "no"))
(ne (symbol_ref "bundling_p") (const_int 0))) (ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01") "2b_M_only_um01")
(define_insn_reservation "2b_ldc" 0
(and (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "ld"))
(eq_attr "check_load" "yes"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01")
(define_insn_reservation "2b_long_i" 1 (define_insn_reservation "2b_long_i" 1
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "long_i")) (eq_attr "itanium_class" "long_i"))
...@@ -1714,11 +1790,23 @@ ...@@ -1714,11 +1790,23 @@
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "xtd")) (eq_attr "itanium_class" "xtd"))
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
(define_insn_reservation "2b_chk_s" 0
(define_insn_reservation "2b_chk_s_i" 0
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "chk_s")) (eq_attr "itanium_class" "chk_s_i"))
(ne (symbol_ref "bundling_p") (const_int 0))) (ne (symbol_ref "bundling_p") (const_int 0)))
"2b_I|2b_M_only_um23") "2b_I|2b_M_only_um23")
(define_insn_reservation "2b_chk_s_f" 0
(and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "chk_s_f"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um23")
(define_insn_reservation "2b_chk_a" 0
(and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "chk_a"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"2b_M_only_um01")
(define_insn_reservation "2b_lfetch" 0 (define_insn_reservation "2b_lfetch" 0
(and (and (eq_attr "cpu" "itanium2") (and (and (eq_attr "cpu" "itanium2")
(eq_attr "itanium_class" "lfetch")) (eq_attr "itanium_class" "lfetch"))
......
gcc/doc/invoke.texi
...@@ -549,7 +549,13 @@ Objective-C and Objective-C++ Dialects}. ...@@ -549,7 +549,13 @@ Objective-C and Objective-C++ Dialects}.
-minline-sqrt-min-latency -minline-sqrt-max-throughput @gol -minline-sqrt-min-latency -minline-sqrt-max-throughput @gol
-mno-dwarf2-asm -mearly-stop-bits @gol -mno-dwarf2-asm -mearly-stop-bits @gol
-mfixed-range=@var{register-range} -mtls-size=@var{tls-size} @gol -mfixed-range=@var{register-range} -mtls-size=@var{tls-size} @gol
-mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64} -mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64 @gol
-mno-sched-br-data-spec -msched-ar-data-spec -mno-sched-control-spec @gol
-msched-br-in-data-spec -msched-ar-in-data-spec -msched-in-control-spec @gol
-msched-ldc -mno-sched-control-ldc -mno-sched-spec-verbose @gol
-mno-sched-prefer-non-data-spec-insns @gol
-mno-sched-prefer-non-control-spec-insns @gol
-mno-sched-count-spec-in-critical-path}
@emph{M32R/D Options} @emph{M32R/D Options}
@gccoptlist{-m32r2 -m32rx -m32r @gol @gccoptlist{-m32r2 -m32rx -m32r @gol
...@@ -9734,6 +9740,113 @@ The 32-bit environment sets int, long and pointer to 32 bits. ...@@ -9734,6 +9740,113 @@ The 32-bit environment sets int, long and pointer to 32 bits.
The 64-bit environment sets int to 32 bits and long and pointer The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits. These are HP-UX specific flags. to 64 bits. These are HP-UX specific flags.
@item -mno-sched-br-data-spec
@itemx -msched-br-data-spec
@opindex -mno-sched-br-data-spec
@opindex -msched-br-data-spec
(Dis/En)able data speculative scheduling before reload.
This will result in generation of the ld.a instructions and
the corresponding check instructions (ld.c / chk.a).
The default is 'disable'.
@item -msched-ar-data-spec
@itemx -mno-sched-ar-data-spec
@opindex -msched-ar-data-spec
@opindex -mno-sched-ar-data-spec
(En/Dis)able data speculative scheduling after reload.
This will result in generation of the ld.a instructions and
the corresponding check instructions (ld.c / chk.a).
The default is 'enable'.
@item -mno-sched-control-spec
@itemx -msched-control-spec
@opindex -mno-sched-control-spec
@opindex -msched-control-spec
(Dis/En)able control speculative scheduling. This feature is
available only during region scheduling (i.e. before reload).
This will result in generation of the ld.s instructions and
the corresponding check instructions chk.s .
The default is 'disable'.
@item -msched-br-in-data-spec
@itemx -mno-sched-br-in-data-spec
@opindex -msched-br-in-data-spec
@opindex -mno-sched-br-in-data-spec
(En/Dis)able speculative scheduling of the instructions that
are dependent on the data speculative loads before reload.
This is effective only with @option{-msched-br-data-spec} enabled.
The default is 'enable'.
@item -msched-ar-in-data-spec
@itemx -mno-sched-ar-in-data-spec
@opindex -msched-ar-in-data-spec
@opindex -mno-sched-ar-in-data-spec
(En/Dis)able speculative scheduling of the instructions that
are dependent on the data speculative loads after reload.
This is effective only with @option{-msched-ar-data-spec} enabled.
The default is 'enable'.
@item -msched-in-control-spec
@itemx -mno-sched-in-control-spec
@opindex -msched-in-control-spec
@opindex -mno-sched-in-control-spec
(En/Dis)able speculative scheduling of the instructions that
are dependent on the control speculative loads.
This is effective only with @option{-msched-control-spec} enabled.
The default is 'enable'.
@item -msched-ldc
@itemx -mno-sched-ldc
@opindex -msched-ldc
@opindex -mno-sched-ldc
(En/Dis)able use of simple data speculation checks ld.c .
If disabled, only chk.a instructions will be emitted to check
data speculative loads.
The default is 'enable'.
@item -mno-sched-control-ldc
@itemx -msched-control-ldc
@opindex -mno-sched-control-ldc
@opindex -msched-control-ldc
(Dis/En)able use of ld.c instructions to check control speculative loads.
If enabled, in case of control speculative load with no speculatively
scheduled dependent instructions this load will be emitted as ld.sa and
ld.c will be used to check it.
The default is 'disable'.
@item -mno-sched-spec-verbose
@itemx -msched-spec-verbose
@opindex -mno-sched-spec-verbose
@opindex -msched-spec-verbose
(Dis/En)able printing of the information about speculative motions.
@item -mno-sched-prefer-non-data-spec-insns
@itemx -msched-prefer-non-data-spec-insns
@opindex -mno-sched-prefer-non-data-spec-insns
@opindex -msched-prefer-non-data-spec-insns
If enabled, data speculative instructions will be choosen for schedule
only if there are no other choices at the moment. This will make
the use of the data speculation much more conservative.
The default is 'disable'.
@item -mno-sched-prefer-non-control-spec-insns
@itemx -msched-prefer-non-control-spec-insns
@opindex -mno-sched-prefer-non-control-spec-insns
@opindex -msched-prefer-non-control-spec-insns
If enabled, control speculative instructions will be choosen for schedule
only if there are no other choices at the moment. This will make
the use of the control speculation much more conservative.
The default is 'disable'.
@item -mno-sched-count-spec-in-critical-path
@itemx -msched-count-spec-in-critical-path
@opindex -mno-sched-count-spec-in-critical-path
@opindex -msched-count-spec-in-critical-path
If enabled, speculative depedencies will be considered during
computation of the instructions priorities. This will make the use of the
speculation a bit more conservative.
The default is 'disable'.
@end table @end table
@node M32C Options @node M32C Options
......
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