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lvzhengyang
riscv-gcc-1
Commits
0488fa7c
Commit
0488fa7c
authored
Oct 11, 2002
by
Joern Rennecke
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From-SVN: r58050
parent
d92b6b94
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4 changed files
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25 additions
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+25
-0
gcc/ChangeLog
+5
-0
gcc/emit-rtl.c
+4
-0
gcc/testsuite/ChangeLog
+4
-0
gcc/testsuite/gcc.c-torture/compile/simd-5.c
+12
-0
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gcc/ChangeLog
View file @
0488fa7c
Fri
Oct
11
10
:
56
:
17
2002
J
"orn Rennecke <joern.rennecke@superh.com>
* emit-rtl.c (gen_lowpart_common): When asked to make a vector from
an integer, use simplify_gen_subreg.
2002-10-10 Aldy Hernandez <aldyh@redhat.com>
* extend.texi (Vector Extensions): Remove comment about single
...
...
gcc/emit-rtl.c
View file @
0488fa7c
...
...
@@ -999,6 +999,10 @@ gen_lowpart_common (mode, x)
else
if
(
GET_CODE
(
x
)
==
SUBREG
||
GET_CODE
(
x
)
==
REG
||
GET_CODE
(
x
)
==
CONCAT
||
GET_CODE
(
x
)
==
CONST_VECTOR
)
return
simplify_gen_subreg
(
mode
,
x
,
GET_MODE
(
x
),
offset
);
else
if
((
GET_MODE_CLASS
(
mode
)
==
MODE_VECTOR_INT
||
GET_MODE_CLASS
(
mode
)
==
MODE_VECTOR_FLOAT
)
&&
GET_MODE
(
x
)
==
VOIDmode
)
return
simplify_gen_subreg
(
mode
,
x
,
int_mode_for_mode
(
mode
),
offset
);
/* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits
from the low-order part of the constant. */
else
if
((
GET_MODE_CLASS
(
mode
)
==
MODE_INT
...
...
gcc/testsuite/ChangeLog
View file @
0488fa7c
Fri Oct 11 10:56:49 2002 Richard Shann <richard.shann@superh.com>
* gcc.c-torture/compile/simd-5.c: New test.
2002-10-10 Jim Wilson <wilson@redhat.com>
* gcc.c-torture/execute/20021010-1.c: New test.
...
...
gcc/testsuite/gcc.c-torture/compile/simd-5.c
0 → 100644
View file @
0488fa7c
#define vector64 __attribute__((vector_size(8)))
main
(){
vector64
int
c
;
vector64
int
a
=
{
1
,
-
1
};
vector64
int
b
=
{
2
,
-
2
};
c
=
-
a
+
b
*
b
*
(
-
1LL
);
/* c is now {5, 3} */
printf
(
"result is %llx
\n
"
,
(
long
long
)
c
);
}
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