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Commit 0462169c by Sofiane Naci Committed by James Greenhalgh
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aarch64.md (define_attr "sync_*"): Remove. 

gcc/
	* config/aarch64/aarch64.md
	(define_attr "sync_*"): Remove.
	(define_attr "length"): Update.
	Include atomics.md.
	* config/aarch64/aarch64-protos.h
	(aarch64_expand_compare_and_swap): Add function prototype.
	(aarch64_split_compare_and_swap): Likewise.
	(aarch64_split_atomic_op): Likewise.
	(aarch64_expand_sync): Remove function prototype.
	(aarch64_output_sync_insn): Likewise.
	(aarch64_output_sync_lock_release): Likewise.
	(aarch64_sync_loop_insns): Likewise.
	(struct aarch64_sync_generator): Remove.
	(enum aarch64_sync_generator_tag): Likewise.
	* config/aarch64/aarch64.c
	(aarch64_legitimize_sync_memory): Remove function.
	(aarch64_emit): Likewise.
	(aarch64_insn_count): Likewise.
	(aarch64_output_asm_insn): Likewise.
	(aarch64_load_store_suffix): Likewise.
	(aarch64_output_sync_load): Likewise.
	(aarch64_output_sync_store): Likewise.
	(aarch64_output_op2): Likewise.
	(aarch64_output_op3): Likewise.
	(aarch64_output_sync_loop): Likewise.
	(aarch64_get_sync_operand): Likewise.
	(aarch64_process_output_sync_insn): Likewise.
	(aarch64_output_sync_insn): Likewise.
	(aarch64_output_sync_lock_release): Likewise.
	(aarch64_sync_loop_insns): Likewise.
	(aarch64_call_generator): Likewise.
	(aarch64_expand_sync): Likewise.
	(* emit_f): Remove variable.
	(aarch64_insn_count): Likewise.
	(FETCH_SYNC_OPERAND): Likewise.
	(aarch64_emit_load_exclusive): New function.
	(aarch64_emit_store_exclusive): Likewise.
	(aarch64_emit_unlikely_jump): Likewise.
	(aarch64_expand_compare_and_swap): Likewise.
	(aarch64_split_compare_and_swap): Likewise.
	(aarch64_split_atomic_op): Likewise.
	* config/aarch64/iterators.md
	(atomic_sfx): New mode attribute.
	(atomic_optab): New code attribute.
	(atomic_op_operand): Likewise.
	(atomic_op_str): Likewise.
	(syncop): Rename to atomic_op.
	* config/aarch64/sync.md: Delete.
	* config/aarch64/atomics.md: New file.

gcc/testsuite
	* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: New testcase.
	* gcc.target/aarch64/atomic-op-acq_rel.c: Likewise.
	* gcc.target/aarch64/atomic-op-acquire.c: Likewise.
	* gcc.target/aarch64/atomic-op-char.c: Likewise.
	* gcc.target/aarch64/atomic-op-consume.c: Likewise.
	* gcc.target/aarch64/atomic-op-imm.c: Likewise.
	* gcc.target/aarch64/atomic-op-int.c: Likewise.
	* gcc.target/aarch64/atomic-op-long.c: Likewise.
	* gcc.target/aarch64/atomic-op-relaxed.c: Likewise.
	* gcc.target/aarch64/atomic-op-release.c: Likewise.
	* gcc.target/aarch64/atomic-op-seq_cst.c: Likewise.
	* gcc.target/aarch64/atomic-op-short.c: Likewise.

From-SVN: r193651
parent 206604dc
Showing with 89 additions and 94 deletions
gcc/ChangeLog
2012-11-20 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md
(define_attr "sync_*"): Remove.
(define_attr "length"): Update.
Include atomics.md.
* config/aarch64/aarch64-protos.h
(aarch64_expand_compare_and_swap): Add function prototype.
(aarch64_split_compare_and_swap): Likewise.
(aarch64_split_atomic_op): Likewise.
(aarch64_expand_sync): Remove function prototype.
(aarch64_output_sync_insn): Likewise.
(aarch64_output_sync_lock_release): Likewise.
(aarch64_sync_loop_insns): Likewise.
(struct aarch64_sync_generator): Remove.
(enum aarch64_sync_generator_tag): Likewise.
* config/aarch64/aarch64.c
(aarch64_legitimize_sync_memory): Remove function.
(aarch64_emit): Likewise.
(aarch64_insn_count): Likewise.
(aarch64_output_asm_insn): Likewise.
(aarch64_load_store_suffix): Likewise.
(aarch64_output_sync_load): Likewise.
(aarch64_output_sync_store): Likewise.
(aarch64_output_op2): Likewise.
(aarch64_output_op3): Likewise.
(aarch64_output_sync_loop): Likewise.
(aarch64_get_sync_operand): Likewise.
(aarch64_process_output_sync_insn): Likewise.
(aarch64_output_sync_insn): Likewise.
(aarch64_output_sync_lock_release): Likewise.
(aarch64_sync_loop_insns): Likewise.
(aarch64_call_generator): Likewise.
(aarch64_expand_sync): Likewise.
(* emit_f): Remove variable.
(aarch64_insn_count): Likewise.
(FETCH_SYNC_OPERAND): Likewise.
(aarch64_emit_load_exclusive): New function.
(aarch64_emit_store_exclusive): Likewise.
(aarch64_emit_unlikely_jump): Likewise.
(aarch64_expand_compare_and_swap): Likewise.
(aarch64_split_compare_and_swap): Likewise.
(aarch64_split_atomic_op): Likewise.
* config/aarch64/iterators.md
(atomic_sfx): New mode attribute.
(atomic_optab): New code attribute.
(atomic_op_operand): Likewise.
(atomic_op_str): Likewise.
(syncop): Rename to atomic_op.
* config/aarch64/sync.md: Delete.
* config/aarch64/atomics.md: New file.
2012-11-20 Jakub Jelinek <jakub@redhat.com> 2012-11-20 Jakub Jelinek <jakub@redhat.com>
PR middle-end/55094 PR middle-end/55094
gcc/config/aarch64/aarch64-protos.h
...@@ -22,35 +22,6 @@ ...@@ -22,35 +22,6 @@
#ifndef GCC_AARCH64_PROTOS_H #ifndef GCC_AARCH64_PROTOS_H
#define GCC_AARCH64_PROTOS_H #define GCC_AARCH64_PROTOS_H
/* This generator struct and enum is used to wrap a function pointer
to a function that generates an RTX fragment but takes either 3 or
4 operands.
The omn flavour, wraps a function that generates a synchronization
instruction from 3 operands: old value, memory and new value.
The omrn flavour, wraps a function that generates a synchronization
instruction from 4 operands: old value, memory, required value and
new value. */
enum aarch64_sync_generator_tag
{
aarch64_sync_generator_omn,
aarch64_sync_generator_omrn
};
/* Wrapper to pass around a polymorphic pointer to a sync instruction
generator and. */
struct aarch64_sync_generator
{
enum aarch64_sync_generator_tag op;
union
{
rtx (*omn) (rtx, rtx, rtx);
rtx (*omrn) (rtx, rtx, rtx, rtx);
} u;
};
/* /*
SYMBOL_CONTEXT_ADR SYMBOL_CONTEXT_ADR
The symbol is used in a load-address operation. The symbol is used in a load-address operation.
...@@ -186,8 +157,6 @@ bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, ...@@ -186,8 +157,6 @@ bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context,
enum aarch64_symbol_type *); enum aarch64_symbol_type *);
bool aarch64_uimm12_shift (HOST_WIDE_INT); bool aarch64_uimm12_shift (HOST_WIDE_INT);
const char *aarch64_output_casesi (rtx *); const char *aarch64_output_casesi (rtx *);
const char *aarch64_output_sync_insn (rtx, rtx *);
const char *aarch64_output_sync_lock_release (rtx, rtx);
enum aarch64_symbol_type aarch64_classify_symbol (rtx, enum aarch64_symbol_type aarch64_classify_symbol (rtx,
enum aarch64_symbol_context); enum aarch64_symbol_context);
enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
...@@ -210,14 +179,11 @@ rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool); ...@@ -210,14 +179,11 @@ rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool);
rtx aarch64_tls_get_addr (void); rtx aarch64_tls_get_addr (void);
unsigned aarch64_dbx_register_number (unsigned); unsigned aarch64_dbx_register_number (unsigned);
unsigned aarch64_trampoline_size (void); unsigned aarch64_trampoline_size (void);
unsigned aarch64_sync_loop_insns (rtx, rtx *);
void aarch64_asm_output_labelref (FILE *, const char *); void aarch64_asm_output_labelref (FILE *, const char *);
void aarch64_elf_asm_named_section (const char *, unsigned, tree); void aarch64_elf_asm_named_section (const char *, unsigned, tree);
void aarch64_expand_epilogue (bool); void aarch64_expand_epilogue (bool);
void aarch64_expand_mov_immediate (rtx, rtx); void aarch64_expand_mov_immediate (rtx, rtx);
void aarch64_expand_prologue (void); void aarch64_expand_prologue (void);
void aarch64_expand_sync (enum machine_mode, struct aarch64_sync_generator *,
rtx, rtx, rtx, rtx);
void aarch64_function_profiler (FILE *, int); void aarch64_function_profiler (FILE *, int);
void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
const_tree, unsigned); const_tree, unsigned);
...@@ -256,6 +222,10 @@ enum machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); ...@@ -256,6 +222,10 @@ enum machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
rtx aarch64_load_tp (rtx); rtx aarch64_load_tp (rtx);
void aarch64_expand_compare_and_swap (rtx op[]);
void aarch64_split_compare_and_swap (rtx op[]);
void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
#endif /* RTX_CODE */ #endif /* RTX_CODE */
#endif /* GCC_AARCH64_PROTOS_H */ #endif /* GCC_AARCH64_PROTOS_H */
gcc/config/aarch64/aarch64.md
...@@ -104,60 +104,6 @@ ...@@ -104,60 +104,6 @@
(include "iterators.md") (include "iterators.md")
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
;; Synchronization Builtins
;; -------------------------------------------------------------------
;; The following sync_* attributes are applied to sychronization
;; instruction patterns to control the way in which the
;; synchronization loop is expanded.
;; All instruction patterns that call aarch64_output_sync_insn ()
;; should define these attributes. Refer to the comment above
;; aarch64.c:aarch64_output_sync_loop () for more detail on the use of
;; these attributes.
;; Attribute specifies the operand number which contains the
;; result of a synchronization operation. The result is the old value
;; loaded from SYNC_MEMORY.
(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none"))
;; Attribute specifies the operand number which contains the memory
;; address to which the synchronization operation is being applied.
(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none"))
;; Attribute specifies the operand number which contains the required
;; old value expected in the memory location. This attribute may be
;; none if no required value test should be performed in the expanded
;; code.
(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none"))
;; Attribute specifies the operand number of the new value to be stored
;; into the memory location identitifed by the sync_memory attribute.
(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none"))
;; Attribute specifies the operand number of a temporary register
;; which can be clobbered by the synchronization instruction sequence.
;; The register provided byn SYNC_T1 may be the same as SYNC_RESULT is
;; which case the result value will be clobbered and not available
;; after the synchronization loop exits.
(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none"))
;; Attribute specifies the operand number of a temporary register
;; which can be clobbered by the synchronization instruction sequence.
;; This register is used to collect the result of a store exclusive
;; instruction.
(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none"))
;; Attribute that specifies whether or not the emitted synchronization
;; loop must contain a release barrier.
(define_attr "sync_release_barrier" "yes,no" (const_string "yes"))
;; Attribute that specifies the operation that the synchronization
;; loop should apply to the old and new values to generate the value
;; written back to memory.
(define_attr "sync_op" "none,add,sub,ior,xor,and,nand"
(const_string "none"))
;; -------------------------------------------------------------------
;; Instruction types and attributes ;; Instruction types and attributes
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
...@@ -370,9 +316,7 @@ ...@@ -370,9 +316,7 @@
(define_attr "simd" "no,yes" (const_string "no")) (define_attr "simd" "no,yes" (const_string "no"))
(define_attr "length" "" (define_attr "length" ""
(cond [(not (eq_attr "sync_memory" "none")) (const_int 4))
(symbol_ref "aarch64_sync_loop_insns (insn, operands) * 4")
] (const_int 4)))
;; Attribute that controls whether an alternative is enabled or not. ;; Attribute that controls whether an alternative is enabled or not.
;; Currently it is only used to disable alternatives which touch fp or simd ;; Currently it is only used to disable alternatives which touch fp or simd
...@@ -2952,5 +2896,5 @@ ...@@ -2952,5 +2896,5 @@
;; AdvSIMD Stuff ;; AdvSIMD Stuff
(include "aarch64-simd.md") (include "aarch64-simd.md")
;; Synchronization Builtins ;; Atomic Operations
(include "sync.md") (include "atomics.md")
gcc/config/aarch64/iterators.md
...@@ -449,6 +449,10 @@ ...@@ -449,6 +449,10 @@
(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")]) (define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
;; Mode for atomic operation suffixes
(define_mode_attr atomic_sfx
[(QI "b") (HI "h") (SI "") (DI "")])
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
;; Code Iterators ;; Code Iterators
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
...@@ -480,7 +484,7 @@ ...@@ -480,7 +484,7 @@
;; Iterator for __sync_<op> operations that where the operation can be ;; Iterator for __sync_<op> operations that where the operation can be
;; represented directly RTL. This is all of the sync operations bar ;; represented directly RTL. This is all of the sync operations bar
;; nand. ;; nand.
(define_code_iterator syncop [plus minus ior xor and]) (define_code_iterator atomic_op [plus minus ior xor and])
;; Iterator for integer conversions ;; Iterator for integer conversions
(define_code_iterator FIXUORS [fix unsigned_fix]) (define_code_iterator FIXUORS [fix unsigned_fix])
...@@ -575,6 +579,16 @@ ...@@ -575,6 +579,16 @@
;; MLA/MLS attributes. ;; MLA/MLS attributes.
(define_code_attr as [(ss_plus "a") (ss_minus "s")]) (define_code_attr as [(ss_plus "a") (ss_minus "s")])
;; Atomic operations
(define_code_attr atomic_optab
[(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
(define_code_attr atomic_op_operand
[(ior "aarch64_logical_operand")
(xor "aarch64_logical_operand")
(and "aarch64_logical_operand")
(plus "aarch64_plus_operand")
(minus "aarch64_plus_operand")])
;; ------------------------------------------------------------------- ;; -------------------------------------------------------------------
;; Int Iterators. ;; Int Iterators.
......
gcc/testsuite/ChangeLog
2012-11-20 Sofiane Naci <sofiane.naci@arm.com>
* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: New testcase.
* gcc.target/aarch64/atomic-op-acq_rel.c: Likewise.
* gcc.target/aarch64/atomic-op-acquire.c: Likewise.
* gcc.target/aarch64/atomic-op-char.c: Likewise.
* gcc.target/aarch64/atomic-op-consume.c: Likewise.
* gcc.target/aarch64/atomic-op-imm.c: Likewise.
* gcc.target/aarch64/atomic-op-int.c: Likewise.
* gcc.target/aarch64/atomic-op-long.c: Likewise.
* gcc.target/aarch64/atomic-op-relaxed.c: Likewise.
* gcc.target/aarch64/atomic-op-release.c: Likewise.
* gcc.target/aarch64/atomic-op-seq_cst.c: Likewise.
* gcc.target/aarch64/atomic-op-short.c: Likewise.
2012-11-20 Jakub Jelinek <jakub@redhat.com> 2012-11-20 Jakub Jelinek <jakub@redhat.com>
PR middle-end/55094 PR middle-end/55094
......
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