Do not do insv/extz on 1/2 byte structures

From-SVN: r9758

gcc/config/rs6000/rs6000.md

@@ -1929,7 +1929,23 @@
 
 ;; Rotate and shift insns, in all their variants.  These support shifts,
 ;; field inserts and extracts, and various combinations thereof.
-(define_insn "insv"
+(define_expand "insv"
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (match_operand:SI 1 "const_int_operand" "i")
+			 (match_operand:SI 2 "const_int_operand" "i"))
+	(match_operand:SI 3 "gpc_reg_operand" "r"))]
+  ""
+  "
+{
+  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
+     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
+     compiler if the address of the structure is taken later.  */
+  if (GET_CODE (operands[0]) == SUBREG
+      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
+    FAIL;
+}")
+
+(define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (match_operand:SI 1 "const_int_operand" "i")
 			 (match_operand:SI 2 "const_int_operand" "i"))
@@ -2021,7 +2037,23 @@
   return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
 }")
 
-(define_insn "extzv"
+(define_expand "extzv"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			 (match_operand:SI 2 "const_int_operand" "i")
+			 (match_operand:SI 3 "const_int_operand" "i")))]
+  ""
+  "
+{
+  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
+     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
+     compiler if the address of the structure is taken later.  */
+  if (GET_CODE (operands[0]) == SUBREG
+      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
+    FAIL;
+}")
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "const_int_operand" "i")