[ARC] Improve code gen when compiling for size

When optimizing for size, try to avoid using long immediate by
employing alternative instructions.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/arc/arc-protos.h (arc_check_ior_const): Declare.
        (arc_split_ior): Likewise.
        (arc_check_mov_const): Likewise.
        (arc_split_mov_const): Likewise.
        * config/arc/arc.c (arc_print_operand): Fix 'z' letter.
        (arc_rtx_costs): Replace check Crr with Cax constraint.
        (prepare_move_operands): Cleanup, remove unused code.
        (arc_split_ior): New function.
        (arc_check_ior_const): Likewise.
        (arc_split_mov_const): Likewise.
        (arc_check_mov_const): Likewise.
        * config/arc/arc.md (movsi_insn): Restructure it, and convert it
        in define_insn_and_split pattern.
        (iorsi3): Likewise.
        (mulsi3_v2): Add new matching variant.
        (andsi3_i): Cleanup pattern.
        (rotrsi3_cnt1): Update pattern.
        (rotrsi3_cnt8): New pattern.
        (ashlsi2_cnt8): Likewise.
        (ashlsi2_cnt16): Likewise.
        * config/arc/constraints.md (C0p): Update constraint.
        (Crr): Remove it.
        (C0x): New pattern.
        (Cax): New pattern.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

        * gcc.target/arc/and-cnst-size.c: New test.
        * gcc.target/arc/mov-cnst-size.c: Likewise.
        * gcc.target/arc/or-cnst-size.c: Likewise.
        * gcc.target/arc/store-merge-1.c: Update test.
        * gcc.target/arc/arc700-stld-hazard.c: Likewise.
        * gcc.target/arc/cmem-1.c: Likewise.
        * gcc.target/arc/cmem-2.c: Likewise.
        * gcc.target/arc/cmem-3.c: Likewise.
        * gcc.target/arc/cmem-4.c: Likewise.
        * gcc.target/arc/cmem-5.c: Likewise.
        * gcc.target/arc/cmem-6.c: Likewise.
        * gcc.target/arc/loop-4.c: Likewise.
        * gcc.target/arc/movh_cl-1.c: Likewise.
        * gcc.target/arc/sdata-3.c: Likewise.

From-SVN: r272112

gcc/ChangeLog

+2019-06-10  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc-protos.h (arc_check_ior_const): Declare.
+	(arc_split_ior): Likewise.
+	(arc_check_mov_const): Likewise.
+	(arc_split_mov_const): Likewise.
+	* config/arc/arc.c (arc_print_operand): Fix 'z' letter.
+	(arc_rtx_costs): Replace check Crr with Cax constraint.
+	(prepare_move_operands): Cleanup, remove unused code.
+	(arc_split_ior): New function.
+	(arc_check_ior_const): Likewise.
+	(arc_split_mov_const): Likewise.
+	(arc_check_mov_const): Likewise.
+	* config/arc/arc.md (movsi_insn): Restructure it, and convert it
+	in define_insn_and_split pattern.
+	(iorsi3): Likewise.
+	(mulsi3_v2): Add new matching variant.
+	(andsi3_i): Cleanup pattern.
+	(rotrsi3_cnt1): Update pattern.
+	(rotrsi3_cnt8): New pattern.
+	(ashlsi2_cnt8): Likewise.
+	(ashlsi2_cnt16): Likewise.
+	* config/arc/constraints.md (C0p): Update constraint.
+	(Crr): Remove it.
+	(C0x): New pattern.
+	(Cax): New pattern.
+
 2019-06-10  Martin Liska  <mliska@suse.cz>
 
 	* ipa-icf.c (sem_item_optimizer::parse_nonsingleton_classes):

gcc/config/arc/arc-protos.h

@@ -48,6 +48,10 @@ extern bool arc_is_uncached_mem_p (rtx);
 extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
 extern bool arc_check_multi (rtx, bool);
 extern void arc_adjust_reg_alloc_order (void);
+extern bool arc_check_ior_const (HOST_WIDE_INT );
+extern void arc_split_ior (rtx *);
+extern bool arc_check_mov_const (HOST_WIDE_INT );
+extern bool arc_split_mov_const (rtx *);
 #endif /* RTX_CODE */
 
 extern unsigned int arc_compute_frame_size (int);

gcc/config/arc/arc.c

@@ -4223,7 +4223,7 @@ arc_print_operand (FILE *file, rtx x, int code)
 
     case 'z':
       if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "%d",exact_log2(INTVAL (x)) );
+	fprintf (file, "%d",exact_log2 (INTVAL (x) & 0xffffffff));
       else
 	output_operand_lossage ("invalid operand to %%z code");
 
@@ -5588,9 +5588,6 @@ arc_rtx_costs (rtx x, machine_mode mode, int outer_code,
 		if (satisfies_constraint_C0p (x)) /* bxor */
 		  nolimm = fast = condexec = true;
 		break;
-	      case SET:
-		if (satisfies_constraint_Crr (x)) /* ror b,u6 */
-		  nolimm = true;
 	      default:
 		break;
 	      }
@@ -9079,31 +9076,6 @@ prepare_move_operands (rtx *operands, machine_mode mode)
 	  MEM_COPY_ATTRIBUTES (pat, operands[0]);
 	  operands[0] = pat;
 	}
-      if (!cse_not_expected)
-	{
-	  rtx pat = XEXP (operands[0], 0);
-
-	  pat = arc_legitimize_address_0 (pat, pat, mode);
-	  if (pat)
-	    {
-	      pat = change_address (operands[0], mode, pat);
-	      MEM_COPY_ATTRIBUTES (pat, operands[0]);
-	      operands[0] = pat;
-	    }
-	}
-    }
-
-  if (MEM_P (operands[1]) && !cse_not_expected)
-    {
-      rtx pat = XEXP (operands[1], 0);
-
-      pat = arc_legitimize_address_0 (pat, pat, mode);
-      if (pat)
-	{
-	  pat = change_address (operands[1], mode, pat);
-	  MEM_COPY_ATTRIBUTES (pat, operands[1]);
-	  operands[1] = pat;
-	}
     }
 
   return false;
@@ -11448,6 +11420,198 @@ arc_memory_move_cost (machine_mode mode,
   return (2 * GET_MODE_SIZE (mode));
 }
 
+/* Split an OR instruction into multiple BSET/OR instructions in a
+   attempt to avoid long immediate constants.  The next strategies are
+   employed when destination is 'q' reg.
+
+   1. if there are up to three bits set in the mask, a succession of
+   three bset instruction will be emitted:
+   OR rA, rB, mask ->
+   BSET(_S) rA,rB,mask1/BSET_S rA,rA,mask2/BSET_S rA,rA,mask3
+
+   2. if the lower 6 bits of the mask is set and there is only one
+   bit set in the upper remaining bits then we will emit one bset and
+   one OR instruction:
+   OR rA, rB, mask -> OR rA,rB,mask1/BSET_S rA,mask2
+
+   3. otherwise an OR with limm will be emmitted.  */
+
+void
+arc_split_ior (rtx *operands)
+{
+  unsigned HOST_WIDE_INT mask, maskx;
+  rtx op1 = operands[1];
+
+  gcc_assert (CONST_INT_P (operands[2]));
+  mask =  INTVAL (operands[2]) & 0xffffffff;
+
+  if (__builtin_popcount (mask) > 3 || (mask & 0x3f))
+    {
+      maskx = mask & 0x3f;
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
+      op1 = operands[0];
+      mask &= ~maskx;
+    }
+
+  switch (__builtin_popcount (mask))
+    {
+    case 3:
+      maskx = 1 << (__builtin_ffs (mask) - 1);
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
+      mask &= ~maskx;
+      op1 = operands[0];
+      /* FALLTHRU */
+    case 2:
+      maskx = 1 << (__builtin_ffs (mask) - 1);
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
+      mask &= ~maskx;
+      op1 = operands[0];
+      /* FALLTHRU */
+    case 1:
+      maskx = 1 << (__builtin_ffs (mask) - 1);
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
+      break;
+    default:
+      break;
+    }
+}
+
+/* Helper to check C0x constraint.  */
+
+bool
+arc_check_ior_const (HOST_WIDE_INT ival)
+{
+  unsigned int mask = (unsigned int) (ival & 0xffffffff);
+  if (__builtin_popcount (mask) <= 3)
+    return true;
+  if (__builtin_popcount (mask & ~0x3f) <= 1)
+    return true;
+  return false;
+}
+
+/* Split a mov with long immediate instruction into smaller, size
+   friendly instructions.  */
+
+bool
+arc_split_mov_const (rtx *operands)
+{
+  unsigned HOST_WIDE_INT ival;
+  HOST_WIDE_INT shimm;
+  machine_mode mode = GET_MODE (operands[0]);
+
+  /* Manage a constant.  */
+  gcc_assert (CONST_INT_P (operands[1]));
+  ival = INTVAL (operands[1]) & 0xffffffff;
+
+  if (SIGNED_INT12 (ival))
+    return false;
+
+  /* 1. Check if we can just rotate limm by 8 but using ROR8.  */
+  if (TARGET_BARREL_SHIFTER && TARGET_V2
+      && ((ival & ~0x3f000000) == 0))
+    {
+      shimm = (ival >> 24) & 0x3f;
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_ROTATERT (mode, GEN_INT (shimm),
+						GEN_INT (8))));
+      return true;
+    }
+  /* 2. Check if we can just shift by 8 to fit into the u6 of LSL8.  */
+  if (TARGET_BARREL_SHIFTER && TARGET_V2
+      && ((ival & ~0x3f00) == 0))
+    {
+      shimm = (ival >> 8) & 0x3f;
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_ASHIFT (mode, GEN_INT (shimm),
+					      GEN_INT (8))));
+      return true;
+    }
+
+  /* 3. Check if we can just shift by 16 to fit into the u6 of LSL16.  */
+  if (TARGET_BARREL_SHIFTER && TARGET_V2
+      && ((ival & ~0x3f0000) == 0))
+    {
+      shimm = (ival >> 16) & 0x3f;
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_ASHIFT (mode, GEN_INT (shimm),
+					      GEN_INT (16))));
+      return true;
+    }
+
+  /* 4. Check if we can do something like mov_s h,u8 / asl_s ra,h,#nb.  */
+  if (((ival >> (__builtin_ffs (ival) - 1)) & 0xffffff00) == 0
+      && TARGET_BARREL_SHIFTER)
+    {
+      HOST_WIDE_INT shift = __builtin_ffs (ival);
+      shimm = (ival >> (shift - 1)) & 0xff;
+      emit_insn (gen_rtx_SET (operands[0], GEN_INT (shimm)));
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_ASHIFT (mode, operands[0],
+					      GEN_INT (shift - 1))));
+      return true;
+    }
+
+  /* 5. Check if we can just rotate the limm, useful when no barrel
+     shifter is present.  */
+  if ((ival & ~0x8000001f) == 0)
+    {
+      shimm = (ival * 2 + 1) & 0x3f;
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_ROTATERT (mode, GEN_INT (shimm),
+						const1_rtx)));
+      return true;
+    }
+
+  /* 6. Check if we can do something with bmask.  */
+  if (IS_POWEROF2_P (ival + 1))
+    {
+      emit_insn (gen_rtx_SET (operands[0], constm1_rtx));
+      emit_insn (gen_rtx_SET (operands[0],
+			      gen_rtx_AND (mode, operands[0],
+					   GEN_INT (ival))));
+      return true;
+    }
+
+  return false;
+}
+
+/* Helper to check Cax constraint.  */
+
+bool
+arc_check_mov_const (HOST_WIDE_INT ival)
+{
+  ival = ival & 0xffffffff;
+
+  if ((ival & ~0x8000001f) == 0)
+    return true;
+
+  if (IS_POWEROF2_P (ival + 1))
+    return true;
+
+  /* The next rules requires a barrel shifter.  */
+  if (!TARGET_BARREL_SHIFTER)
+    return false;
+
+  if (((ival >> (__builtin_ffs (ival) - 1)) & 0xffffff00) == 0)
+    return true;
+
+  if ((ival & ~0x3f00) == 0)
+    return true;
+
+  if ((ival & ~0x3f0000) == 0)
+    return true;
+
+  if ((ival & ~0x3f000000) == 0)
+    return true;
+
+  return false;
+}
+
+
 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
 

gcc/config/arc/constraints.md

@@ -201,7 +201,7 @@
  "@internal
   power of two"
   (and (match_code "const_int")
-       (match_test "IS_POWEROF2_P (ival)")))
+       (match_test "IS_POWEROF2_P (ival & 0xffffffff)")))
 
 (define_constraint "C1p"
  "@internal
@@ -275,12 +275,6 @@
   (and (match_code "const_int")
        (match_test "ival == 1 || ival == 2 || ival == 4 || ival == 8")))
 
-(define_constraint "Crr"
- "@internal
-  constant that can be loaded with ror b,u6"
-  (and (match_code "const_int")
-       (match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))
-
 (define_constraint "Cbi"
  "@internal
   constant that can be loaded with movbi.cl"
@@ -290,6 +284,20 @@
 		    || ((ival & 0xffffffffUL) >> exact_log2 (ival & -ival)
 			<= 0xff)")))
 
+(define_constraint "C0x"
+  "@internal
+  special const_int pattern used to split ior insns"
+  (and (match_code "const_int")
+       (match_test "optimize_size")
+       (match_test "arc_check_ior_const (ival)")))
+
+(define_constraint "Cax"
+  "@internal
+  special const_int pattern used to split mov insns"
+  (and (match_code "const_int")
+       (match_test "optimize_size")
+       (match_test "arc_check_mov_const (ival)")))
+
 ;; Floating-point constraints
 
 (define_constraint "G"

gcc/testsuite/ChangeLog

+2019-06-10  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* gcc.target/arc/and-cnst-size.c: New test.
+	* gcc.target/arc/mov-cnst-size.c: Likewise.
+	* gcc.target/arc/or-cnst-size.c: Likewise.
+	* gcc.target/arc/store-merge-1.c: Update test.
+	* gcc.target/arc/arc700-stld-hazard.c: Likewise.
+	* gcc.target/arc/cmem-1.c: Likewise.
+	* gcc.target/arc/cmem-2.c: Likewise.
+	* gcc.target/arc/cmem-3.c: Likewise.
+	* gcc.target/arc/cmem-4.c: Likewise.
+	* gcc.target/arc/cmem-5.c: Likewise.
+	* gcc.target/arc/cmem-6.c: Likewise.
+	* gcc.target/arc/loop-4.c: Likewise.
+	* gcc.target/arc/movh_cl-1.c: Likewise.
+	* gcc.target/arc/sdata-3.c: Likewise.
+
 2019-06-10  Martin Liska  <mliska@suse.cz>
 
 	* gcc.dg/ipa/pr68035.c: Update scanned pattern.

gcc/testsuite/gcc.target/arc/and-cnst-size.c

+/* Tests to check if and instructions are emitted efficiently.  */
+/* { dg-require-effective-target codedensity } */
+/* { dg-options "-Os" } */
+
+int check_bclr (int a)
+{
+  return a & (~0x40);
+}
+
+int check_bmskn (int a)
+{
+  return a & (-128);
+}
+
+/* { dg-final { scan-assembler "bclr_s" } } */
+/* { dg-final { scan-assembler "bmskn" } } */

gcc/testsuite/gcc.target/arc/arc700-stld-hazard.c

 /* { dg-do compile } */
-/* { dg-options "-mcpu=arc700 -mno-sdata" } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-mcpu=arc700 -mno-sdata -O2" } */
 
 volatile int a;
 volatile int b;
@@ -11,4 +12,4 @@ foo ()
   b = a;
 }
 
-/* { dg-final { scan-assembler "st r\[0-9\]+,\\\[@a\\\]\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+ld r\[0-9\]+,\\\[@a\\\]" } } */
+/* { dg-final { scan-assembler "st\\s+r\[0-9\]+,\\\[@a\\\]\\.*\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+nop_s\[^\n\]*\n\[ \t\]+ld\\s+r\[0-9\]+,\\\[@a\\\]" } } */

gcc/testsuite/gcc.target/arc/cmem-1.c

@@ -6,6 +6,6 @@
 
 #include "cmem-st.inc"
 
-/* { dg-final { scan-assembler "xst " } } */
-/* { dg-final { scan-assembler "xstw " } } */
-/* { dg-final { scan-assembler "xstb " } } */
+/* { dg-final { scan-assembler "xst\\s" } } */
+/* { dg-final { scan-assembler "xstw\\s" } } */
+/* { dg-final { scan-assembler "xstb\\s" } } */

gcc/testsuite/gcc.target/arc/cmem-2.c

@@ -6,6 +6,6 @@
 
 #include "cmem-ld.inc"
 
-/* { dg-final { scan-assembler "xld " } } */
-/* { dg-final { scan-assembler "xldw " } } */
-/* { dg-final { scan-assembler "xldb " } } */
+/* { dg-final { scan-assembler "xld\\s" } } */
+/* { dg-final { scan-assembler "xldw\\s" } } */
+/* { dg-final { scan-assembler "xldb\\s" } } */

gcc/testsuite/gcc.target/arc/cmem-3.c

@@ -6,6 +6,6 @@
 
 #include "cmem-st.inc"
 
-/* { dg-final { scan-assembler "xst " } } */
-/* { dg-final { scan-assembler "xstw " } } */
-/* { dg-final { scan-assembler "xstb " } } */
+/* { dg-final { scan-assembler "xst\\s" } } */
+/* { dg-final { scan-assembler "xstw\\s" } } */
+/* { dg-final { scan-assembler "xstb\\s" } } */

gcc/testsuite/gcc.target/arc/cmem-4.c

@@ -6,6 +6,6 @@
 
 #include "cmem-ld.inc"
 
-/* { dg-final { scan-assembler "xld " } } */
-/* { dg-final { scan-assembler "xldw " } } */
-/* { dg-final { scan-assembler "xldb " } } */
+/* { dg-final { scan-assembler "xld\\s" } } */
+/* { dg-final { scan-assembler "xldw\\s" } } */
+/* { dg-final { scan-assembler "xldb\\s" } } */

gcc/testsuite/gcc.target/arc/cmem-5.c

@@ -6,6 +6,6 @@
 
 #include "cmem-st.inc"
 
-/* { dg-final { scan-assembler "xst " } } */
-/* { dg-final { scan-assembler "xstw " } } */
-/* { dg-final { scan-assembler "xstb " } } */
+/* { dg-final { scan-assembler "xst\\s" } } */
+/* { dg-final { scan-assembler "xstw\\s" } } */
+/* { dg-final { scan-assembler "xstb\\s" } } */

gcc/testsuite/gcc.target/arc/cmem-6.c

@@ -6,6 +6,6 @@
 
 #include "cmem-ld.inc"
 
-/* { dg-final { scan-assembler "xld " } } */
-/* { dg-final { scan-assembler "xldw " } } */
-/* { dg-final { scan-assembler "xldb " } } */
+/* { dg-final { scan-assembler "xld\\s" } } */
+/* { dg-final { scan-assembler "xldw\\s" } } */
+/* { dg-final { scan-assembler "xldb\\s" } } */

gcc/testsuite/gcc.target/arc/loop-4.c

@@ -3,12 +3,13 @@
 /* { dg-options "-Os -fbranch-count-reg" } */
 
 
-void fn1(void *p1, int p2, int p3)
+int fn1(void *p1, int p2, int p3)
 {
   char *d = p1;
   do
     *d++ = p2;
   while (--p3);
+  return *d;
 }
 
 /* { dg-final { scan-assembler "lp_count" } } */

gcc/testsuite/gcc.target/arc/mov-cnst-size.c

+/* Tests to check if mov instructions are emitted efficiently.  */
+/* { dg-require-effective-target codedensity } */
+/* { dg-options "-Os" } */
+
+int rule1 (void)
+{
+  return 0x3f000000;
+}
+
+int rule2 (void)
+{
+  return 0x3f00;
+}
+
+int rule3 (void)
+{
+  return 0x3f0000;
+}
+
+int rule4 (void)
+{
+  return 0x22000;
+}
+
+int rule5 (void)
+{
+  return 0x8000001f;
+}
+
+int rule6 (void)
+{
+  return 0x3fffff;
+}
+
+/* { dg-final { scan-assembler "ror8\\s+r0,63" } } */
+/* { dg-final { scan-assembler "lsl8\\s+r0,63" } } */
+/* { dg-final { scan-assembler "lsl16\\s+r0,63" } } */
+/* { dg-final { scan-assembler "ror\\s+r0,63" } } */
+/* { dg-final { scan-assembler "mov_s\\s+r0,17" } } */
+/* { dg-final { scan-assembler "asl_s\\s+r0,r0,13" } } */
+/* { dg-final { scan-assembler "mov_s\\s+r0,-1" } } */
+/* { dg-final { scan-assembler "bmsk_s\\s+r0,r0,21" } } */

gcc/testsuite/gcc.target/arc/movh_cl-1.c

@@ -36,4 +36,4 @@ woof ()
   func (xx.raw);
 }
 
-/* { dg-final { scan-assembler "movh\.cl r\[0-9\]+,0xc0000000>>16" } } */
+/* { dg-final { scan-assembler "movh\.cl\\s+r\[0-9\]+,0xc0000000>>16" } } */

gcc/testsuite/gcc.target/arc/or-cnst-size.c

+/* Tests to check if or instructions are emitted efficiently.  */
+/* { dg-require-effective-target codedensity } */
+/* { dg-options "-Os" } */
+
+int check_bset1 (int a)
+{
+  return a | 0x80000000;
+}
+
+int check_bset2(int a)
+{
+  return a | 0x2022;
+}
+
+/* { dg-final { scan-assembler-times "bset_s" 2 } } */
+/* { dg-final { scan-assembler "or" } } */

gcc/testsuite/gcc.target/arc/sdata-3.c

@@ -2,7 +2,7 @@
    for variables which are having a different alignment
    than the default data type indicates.  */
 /* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -msdata" } */
 
 int g_a __attribute__ ((aligned (1)));
 int g_b;
@@ -24,13 +24,13 @@ TEST (b, int)
 TEST (c, short)
 TEST (d, char)
 
-/* { dg-final { scan-assembler "ld r2,\\\[gp,@g_a@sda\\\]" } } */
-/* { dg-final { scan-assembler "ld.as r2,\\\[gp,@g_b@sda\\\]" } } */
-/* { dg-final { scan-assembler "ld\[hw\]\\\.as r2,\\\[gp,@g_c@sda\\\]" } } */
-/* { dg-final { scan-assembler "ldb r2,\\\[gp,@g_d@sda\\\]" } } */
+/* { dg-final { scan-assembler "ld\\s+r2,\\\[gp,@g_a@sda\\\]" } } */
+/* { dg-final { scan-assembler "ld.as\\s+r2,\\\[gp,@g_b@sda\\\]" } } */
+/* { dg-final { scan-assembler "ld\[hw\]\\\.as\\s+r2,\\\[gp,@g_c@sda\\\]" } } */
+/* { dg-final { scan-assembler "ldb\\s+r2,\\\[gp,@g_d@sda\\\]" } } */
 
-/* { dg-final { scan-assembler "st r0,\\\[gp,@g_a@sda\\\]" } } */
-/* { dg-final { scan-assembler "st_s r0,\\\[gp,@g_b@sda\\\]" { target { arcem || archs } } } } */
-/* { dg-final { scan-assembler "st\\\.as r0,\\\[gp,@g_b@sda\\\]" { target { arc700 || arc6xx } } } } */
-/* { dg-final { scan-assembler "st\[hw\]\\\.as r0,\\\[gp,@g_c@sda\\\]" } } */
-/* { dg-final { scan-assembler "stb r0,\\\[gp,@g_d@sda\\\]" } } */
+/* { dg-final { scan-assembler "st\\s+r0,\\\[gp,@g_a@sda\\\]" } } */
+/* { dg-final { scan-assembler "st_s\\s+r0,\\\[gp,@g_b@sda\\\]" { target { codedensity } } } } */
+/* { dg-final { scan-assembler "st\\\.as\\s+r0,\\\[gp,@g_b@sda\\\]" { target { ! { codedensity } } } } } */
+/* { dg-final { scan-assembler "st\[hw\]\\\.as\\s+r0,\\\[gp,@g_c@sda\\\]" } } */
+/* { dg-final { scan-assembler "stb\\s+r0,\\\[gp,@g_d@sda\\\]" } } */

gcc/testsuite/gcc.target/arc/store-merge-1.c

@@ -14,4 +14,4 @@ int sigemptyset2 (sigset_t *set)
   return 0;
 }
 
-/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */
+/* { dg-final { scan-assembler-times "std\\s*0,\\\[r" 1 } } */