Commit 02eb5b8b by Bill Schmidt Committed by William Schmidt

re PR target/71297 (ICE on invalid code in altivec_resolve_overloaded_builtin…

re PR target/71297 (ICE on invalid code in altivec_resolve_overloaded_builtin (rs6000-c.c:5106) on powerpc64le-linux)

[gcc]

2016-07-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/71297
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Allow standard error handling to take over when a wrong number
	of arguments is presented to __builtin_vec_ld () or
	__builtin_vec_st ().

[gcc/testsuite]

2016-07-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/71297
	* gcc.target/powerpc/pr71297.c: New.

From-SVN: r238168
parent 8beb9a0d
2016-07-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/71297
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Allow standard error handling to take over when a wrong number
of arguments is presented to __builtin_vec_ld () or
__builtin_vec_st ().
2016-07-08 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-simd-builtins.def (smax): Remove float
......
......@@ -5281,10 +5281,11 @@ assignment for unaligned loads and stores");
are able to honor __restrict__, for example. We may want to
consider this for all memory access built-ins.
When -maltivec=be is specified, simply punt to existing
built-in processing. */
When -maltivec=be is specified, or the wrong number of arguments
is provided, simply punt to existing built-in processing. */
if (fcode == ALTIVEC_BUILTIN_VEC_LD
&& (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG))
&& (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
&& nargs == 2)
{
tree arg0 = (*arglist)[0];
tree arg1 = (*arglist)[1];
......@@ -5354,7 +5355,8 @@ assignment for unaligned loads and stores");
/* Similarly for stvx. */
if (fcode == ALTIVEC_BUILTIN_VEC_ST
&& (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG))
&& (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
&& nargs == 3)
{
tree arg0 = (*arglist)[0];
tree arg1 = (*arglist)[1];
......
2016-07-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/71297
* gcc.target/powerpc/pr71297.c: New.
2016-07-08 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/simd/vminmaxnm_1.c: New.
......
/* PR target/71763 */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
int main ()
{
__builtin_vec_st (); /* { dg-error "too few arguments to function" } */
}
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