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riscv-gcc-1
Commit 02ca7595 by David Edelsohn Committed by David Edelsohn
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rs6000.md (define_attr "type"): Add mfjmpr. 

        * config/rs6000/rs6000.md (define_attr "type"): Add mfjmpr.
        (movsi_internal1): Use new mfjmpr attribute.
        (movhi_internal): Same.
        (movqi_internal): Same.
        (movcc_internal1): Same.
        (movdi_internal64): Same.
        * config/rs6000/{40x.md,603.md,6xx.md,7450.md,7xx.md,mpc.md,
        power4.md,rios1.md,rios2.md,rs64.md}: Add mfjmpr.
        * config/rs6000/40x.md: Add fpu_405.
        * config/rs6000/power4.md: Merge power4lsu and power4disp automata
        into power4misc automata.  Remove extraneous parentheses.
        * config/rs6000/440.md: New file.
        * config/rs6000/rs6000.c (processor_target_table): Add 440,
        440fp.  Rename 405f to 405fp.
        (function_arg_padding): Correct formatting.
        (rs6000_rtx_costs): Add PROCESSOR_PPC440 cases.

From-SVN: r66336
parent 397751ae
Showing with 292 additions and 61 deletions
gcc/ChangeLog
2003-05-01 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (define_attr "type"): Add mfjmpr.
(movsi_internal1): Use new mfjmpr attribute.
(movhi_internal): Same.
(movqi_internal): Same.
(movcc_internal1): Same.
(movdi_internal64): Same.
* config/rs6000/{40x.md,603.md,6xx.md,7450.md,7xx.md,mpc.md,
power4.md,rios1.md,rios2.md,rs64.md}: Add mfjmpr.
* config/rs6000/40x.md: Add fpu_405.
* config/rs6000/power4.md: Merge power4lsu and power4disp automata
into power4misc automata. Remove extraneous parentheses.
* config/rs6000/440.md: New file.
* config/rs6000/rs6000.c (processor_target_table): Add 440,
440fp. Rename 405f to 405fp.
(function_arg_padding): Correct formatting.
(rs6000_rtx_costs): Add PROCESSOR_PPC440 cases.
2003-05-01 Nathan Sidwell <nathan@codesourcery.com>
* input.h (lineno): Rename to ...
......
gcc/config/rs6000/40x.md
......@@ -19,7 +19,7 @@
;; MA 02111-1307, USA.
(define_automaton "ppc40x")
(define_cpu_unit "iu_40x,bpu_40x" "ppc40x")
(define_cpu_unit "iu_40x,bpu_40x,fpu_405" "ppc40x")
;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
;; Embedded PowerPC controller
......@@ -71,17 +71,37 @@
"iu_40x*33")
(define_insn_reservation "ppc403-mfcr" 2
(and (eq_attr "type" "mfcr,mtcr")
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
"iu_40x")
(define_insn_reservation "ppc403-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
(define_insn_reservation "ppc403-cr" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
(define_insn_reservation "ppc405-float" 11
(and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,fpcompare,fp,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405"))
"fpu_405*10")
gcc/config/rs6000/440.md 0 → 100644
;; Scheduling description for IBM PowerPC 440 processor.
;; Copyright (C) 2003 Free Software Foundation, Inc.
;;
;; This file is part of GNU CC.
;;
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
;; PPC440 Embedded PowerPC controller
;; dual issue
;; i_pipe - complex integer / compare / branch
;; j_pipe - simple integer arithmetic
;; l_pipe - load-store
;; f_pipe - floating point arithmetic
(define_automaton "ppc440_core,ppc440_apu")
(define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
(define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
(define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
(define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
(define_insn_reservation "ppc440-load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 1
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpload" 4
(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
(and (eq_attr "type" "integer")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
(and (eq_attr "type" "imul2,imul3")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-idiv" 34
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe*33")
(define_insn_reservation "ppc440-branch" 1
(and (eq_attr "type" "branch,jmpreg")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
(and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-fpcompare" 3 ; 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
(define_insn_reservation "ppc440-sdiv" 19
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*15")
(define_insn_reservation "ppc440-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*29")
(define_insn_reservation "ppc440-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
gcc/config/rs6000/603.md
......@@ -105,20 +105,20 @@
(eq_attr "cpu" "ppc603"))
"fpu_603*33")
(define_insn_reservation "ppc603-mtcr" 2
(and (eq_attr "type" "mtcr")
(define_insn_reservation "ppc603-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-crlogical" 1
(and (eq_attr "type" "cr_logical,delayed_cr,mfcr")
(define_insn_reservation "ppc603-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(define_insn_reservation "ppc603-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc603"))
"bpu_603")
"sru_603")
(define_insn_reservation "ppc603-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
......
gcc/config/rs6000/6xx.md
......@@ -165,7 +165,7 @@
(define_insn_reservation "ppc630-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc630"))
"(fpu1_6xx|fpu2_6xx)")
"fpu1_6xx|fpu2_6xx")
(define_insn_reservation "ppc630-fp" 3
(and (eq_attr "type" "fp,dmul")
......@@ -200,22 +200,32 @@
(define_insn_reservation "ppc604-mtcr" 2
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"mciu_6xx")
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-crlogical" 1
(define_insn_reservation "ppc604-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc604"))
"bpu_6xx")
(define_insn_reservation "ppc604e-crlogical" 1
(define_insn_reservation "ppc604e-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc604e,ppc620,ppc630"))
"cru_6xx")
(define_insn_reservation "ppc604-mtjmpr" 4
(define_insn_reservation "ppc604-mtjmpr" 2
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"bpu_6xx")
"mciu_6xx")
(define_insn_reservation "ppc604-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"mciu_6xx")
(define_insn_reservation "ppc630-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
......
gcc/config/rs6000/7450.md
......@@ -124,6 +124,11 @@
(eq_attr "cpu" "ppc7450"))
"nothing,mciu_7450*2")
(define_insn_reservation "ppc7450-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc7450"))
"nothing,mciu_7450*2")
(define_insn_reservation "ppc7450-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc7450"))
......
gcc/config/rs6000/7xx.md
......@@ -134,6 +134,11 @@
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc750,ppc7400"))
......
gcc/config/rs6000/8540.md
......@@ -132,7 +132,7 @@
;; Mtjmpr
(define_insn_reservation "ppc8540_mtjmpr" 1
(and (eq_attr "type" "mtjmpr")
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
......
gcc/config/rs6000/mpc.md
......@@ -88,7 +88,7 @@
"fpu_mpc*17")
(define_insn_reservation "mpccore-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "mpccore"))
"bpu_mpc")
......
gcc/config/rs6000/power4.md
......@@ -25,15 +25,15 @@
;; (split) or more internal ops. The chip can issue up to 5
;; internal ops per cycle.
(define_automaton "power4iu,power4lsu,power4fpu,power4misc,power4vec,power4disp")
(define_automaton "power4iu,power4fpu,power4vec,power4misc")
(define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
(define_cpu_unit "lsu1_power4,lsu2_power4" "power4lsu")
(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
(define_cpu_unit "bpu_power4,cru_power4" "power4misc")
(define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
"power4disp")
"power4misc")
(define_reservation "lsq_power4"
"(du1_power4,lsu1_power4)\
......@@ -42,10 +42,10 @@
|(du4_power4,nothing,lsu1_power4)")
(define_reservation "lsuq_power4"
"((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
|((du2_power4+du3_power4),lsu2_power4+iu2_power4)\
|((du3_power4+du4_power4),lsu2_power4+iu1_power4)")
; |((du2_power4+du3_power4),nothing,lsu2_power4,iu2_power4)
"(du1_power4+du2_power4,lsu1_power4+iu2_power4)\
|(du2_power4+du3_power4,lsu2_power4+iu2_power4)\
|(du3_power4+du4_power4,lsu2_power4+iu1_power4)")
; |(du2_power4+du3_power4,nothing,lsu2_power4,iu2_power4)
(define_reservation "iq_power4"
"(du1_power4,iu1_power4)\
......@@ -95,19 +95,19 @@
(define_insn_reservation "power4-load-ext-update" 5
(and (eq_attr "type" "load_ext_u")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4+du3_power4+du4_power4),\
(lsu1_power4+iu2_power4),nothing,nothing,iu2_power4")
"du1_power4+du2_power4+du3_power4+du4_power4,\
lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-ext-update-indexed" 5
(and (eq_attr "type" "load_ext_ux")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4+du3_power4+du4_power4),\
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-update-indexed" 3
(and (eq_attr "type" "load_ux")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4")
(define_insn_reservation "power4-load-update" 4 ; 3
......@@ -253,16 +253,16 @@
(define_insn_reservation "power4-idiv" 36
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4),iu2_power4*35")
"du1_power4+du2_power4,iu2_power4*35")
(define_insn_reservation "power4-ldiv" 68
(and (eq_attr "type" "ldiv")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4),iu2_power4*67")
"du1_power4+du2_power4,iu2_power4*67")
(define_insn_reservation "power4-mtjmpr" 3
(and (eq_attr "type" "mtjmpr")
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "power4"))
"du1_power4,bpu_power4")
......@@ -288,15 +288,15 @@
(define_insn_reservation "power4-delayedcr" 4
(and (eq_attr "type" "delayed_cr")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4),cru_power4,cru_power4")
"du1_power4+du2_power4,cru_power4,cru_power4")
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
(define_insn_reservation "power4-mfcr" 6
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4+du3_power4+du4_power4),\
(du1_power4+du2_power4+du3_power4+du4_power4+cru_power4),\
cru_power4,cru_power4,cru_power4")
"du1_power4+du2_power4+du3_power4+du4_power4,\
du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
cru_power4,cru_power4,cru_power4")
; mtcrf (1 field)
(define_insn_reservation "power4-mtcr" 4
......
gcc/config/rs6000/rios1.md
......@@ -51,7 +51,7 @@
"iu_rios1+fpu_rios1")
(define_insn_reservation "rios1-integer" 1
(and (eq_attr "type" "integer,mfcr,mtcr")
(and (eq_attr "type" "integer")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
......@@ -142,6 +142,16 @@
(eq_attr "cpu" "ppc601"))
"fpu_rios1*31")
(define_insn_reservation "rios1-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1,bpu_rios1")
(define_insn_reservation "rios1-mtcr" 4
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1,bpu_rios1")
(define_insn_reservation "rios1-crlogical" 4
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "rios1,ppc601"))
......@@ -150,12 +160,17 @@
(define_insn_reservation "rios1-mtjmpr" 5
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "rios1"))
"bpu_rios1")
"iu_rios1,bpu_rios1")
(define_insn_reservation "ppc601-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc601"))
"bpu_rios1")
"iu_rios1,bpu_rios1")
(define_insn_reservation "rios1-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1,bpu_rios1")
(define_insn_reservation "rios1-branch" 1
(and (eq_attr "type" "jmpreg,branch")
......
gcc/config/rs6000/rios2.md
......@@ -39,7 +39,7 @@
"iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-integer" 1
(and (eq_attr "type" "integer,mfcr,mtcr")
(and (eq_attr "type" "integer")
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
......@@ -85,7 +85,17 @@
(eq_attr "cpu" "rios2"))
"(fpu1_rios2*26)|(fpu2_rios2*26)")
(define_insn_reservation "rios2-crlogical" 4
(define_insn_reservation "rios2-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "rios2"))
"iu1_rios2,bpu_rios2")
(define_insn_reservation "rios2-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "rios2"))
"iu1_rios2,bpu_rios2")
(define_insn_reservation "rios2-crlogical" 3
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "rios2"))
"bpu_rios2")
......@@ -93,9 +103,14 @@
(define_insn_reservation "rios2-mtjmpr" 5
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "rios2"))
"bpu_rios2")
"iu1_rios2,bpu_rios2")
(define_insn_reservation "rios2-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "rios2"))
"iu1_rios2,bpu_rios2")
(define_insn_reservation "rios2-jmpreg" 1
(define_insn_reservation "rios2-branch" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "rios2"))
"bpu_rios2")
......
gcc/config/rs6000/rs6000.c
......@@ -527,7 +527,13 @@ rs6000_override_options (default_cpu)
{"405", PROCESSOR_PPC405,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"405f", PROCESSOR_PPC405,
{"405fp", PROCESSOR_PPC405,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"440", PROCESSOR_PPC440,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"440fp", PROCESSOR_PPC440,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"505", PROCESSOR_MPCCORE,
......@@ -3175,12 +3181,12 @@ function_arg_padding (mode, type)
/* This is the default definition. */
return (! BYTES_BIG_ENDIAN
? upward
: ((mode == BLKmode
? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
&& int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
: GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
? downward : upward));
? upward
: ((mode == BLKmode
? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
&& int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
: GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
? downward : upward));
}
/* If defined, a C expression that gives the alignment boundary, in bits,
......@@ -13664,6 +13670,12 @@ rs6000_rtx_costs (x, code, outer_code, total)
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
return true;
case PROCESSOR_PPC440:
*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
? COSTS_N_INSNS (3)
: COSTS_N_INSNS (2));
return true;
case PROCESSOR_RS64A:
*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
? GET_MODE (XEXP (x, 1)) != DImode
......@@ -13766,6 +13778,10 @@ rs6000_rtx_costs (x, code, outer_code, total)
*total = COSTS_N_INSNS (35);
return true;
case PROCESSOR_PPC440:
*total = COSTS_N_INSNS (34);
return true;
case PROCESSOR_PPC601:
*total = COSTS_N_INSNS (36);
return true;
......
gcc/config/rs6000/rs6000.md
......@@ -62,7 +62,7 @@
;; Define an insn type attribute. This is used in function unit delay
;; computations.
(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
......@@ -91,6 +91,7 @@
(include "rs64.md")
(include "mpc.md")
(include "40x.md")
(include "440.md")
(include "603.md")
(include "6xx.md")
(include "7xx.md")
......@@ -7682,7 +7683,7 @@
mt%0 %1
mt%0 %1
{cror 0,0,0|nop}"
[(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
[(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
(set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn
......@@ -7751,7 +7752,7 @@
mt%0 %1
mt%0 %1
{cror 0,0,0|nop}"
[(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
[(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "")
......@@ -7773,7 +7774,7 @@
mt%0 %1
mt%0 %1
{cror 0,0,0|nop}"
[(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
[(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
;; Here is how to move condition codes around. When we store CC data in
;; an integer register or memory, we store just the high-order 4 bits.
......@@ -7801,7 +7802,7 @@
mt%0 %1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%U1|stw%U0%U1} %1,%0"
[(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,*,*,mtjmpr,load,store")
[(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,mfjmpr,*,mtjmpr,load,store")
(set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
;; For floating-point, we normally deal with the floating-point registers
......@@ -8556,7 +8557,7 @@
mf%1 %0
mt%0 %1
{cror 0,0,0|nop}"
[(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
[(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
;; immediate value valid for a single instruction hiding in a const_double
......
gcc/config/rs6000/rs64.md
......@@ -104,17 +104,22 @@
(define_insn_reservation "rs64a-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "rs64a"))
"mciu_rs64")
"lsu_rs64")
(define_insn_reservation "rs64a-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "rs64a"))
"mciu_rs64")
"lsu_rs64")
(define_insn_reservation "rs64a-mtjmpr" 5
(define_insn_reservation "rs64a-mtjmpr" 3
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "rs64a"))
"bpu_rs64")
"lsu_rs64")
(define_insn_reservation "rs64a-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
......
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