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riscv-gcc-1
Commit 029e79eb by Marcus Shawcroft Committed by Ramana Radhakrishnan
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For Marcus - Implement sync primitives inline for ARM. 

2010-08-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/arm/arm-protos.h (arm_expand_sync): New.
	(arm_output_memory_barrier, arm_output_sync_insn): New.
	(arm_sync_loop_insns): New.
	* config/arm/arm.c (FL_ARCH7): New.
	(FL_FOR_ARCH7): Include FL_ARCH7.
	(arm_arch7): New.
	(arm_print_operand): Support %C markup.
	(arm_legitimize_sync_memory): New.
	(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
	(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
	(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
	(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
	(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
	(arm_process_output_sync_insn, arm_output_sync_insn): New.
	(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
	* config/arm/arm.h (struct arm_sync_generator): New.
	(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
	(TARGET_HAVE_MEMORY_BARRIER): New.
	(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
	* config/arm/arm.md: Include sync.md.
	(UNSPEC_MEMORY_BARRIER): New.
	(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
	(VUNSPEC_SYNC_OP):New.
	(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
	(sync_result, sync_memory, sync_required_value): New attributes.
	(sync_new_value, sync_t1, sync_t2): Likewise.
	(sync_release_barrier, sync_op): Likewise.
	(length): Add logic to length attribute defintion to call
	arm_sync_loop_insns when appropriate.
	* config/arm/sync.md: New file.

From-SVN: r163327
parent 257f5167
Showing with 98 additions and 2 deletions
gcc/ChangeLog
2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/arm/arm-protos.h (arm_expand_sync): New.
(arm_output_memory_barrier, arm_output_sync_insn): New.
(arm_sync_loop_insns): New.
* config/arm/arm.c (FL_ARCH7): New.
(FL_FOR_ARCH7): Include FL_ARCH7.
(arm_arch7): New.
(arm_print_operand): Support %C markup.
(arm_legitimize_sync_memory): New.
(arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New.
(arm_process_output_memory_barrier, arm_output_memory_barrier): New.
(arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New.
(arm_output_op2, arm_output_op3, arm_output_sync_loop): New.
(arm_get_sync_operand, FETCH_SYNC_OPERAND): New.
(arm_process_output_sync_insn, arm_output_sync_insn): New.
(arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New.
* config/arm/arm.h (struct arm_sync_generator): New.
(TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New.
(TARGET_HAVE_MEMORY_BARRIER): New.
(TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New.
* config/arm/arm.md: Include sync.md.
(UNSPEC_MEMORY_BARRIER): New.
(VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New.
(VUNSPEC_SYNC_OP):New.
(VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New.
(sync_result, sync_memory, sync_required_value): New attributes.
(sync_new_value, sync_t1, sync_t2): Likewise.
(sync_release_barrier, sync_op): Likewise.
(length): Add logic to length attribute defintion to call
arm_sync_loop_insns when appropriate.
* config/arm/sync.md: New file.
2010-08-17 Jakub Jelinek <jakub@redhat.com>
* tree.h (host_integerp): Add ATTRIBUTE_PURE when not
......
gcc/config/arm/arm-protos.h
......@@ -144,6 +144,11 @@ extern const char *vfp_output_fstmd (rtx *);
extern void arm_set_return_address (rtx, rtx);
extern int arm_eliminable_register (rtx);
extern const char *arm_output_shift(rtx *, int);
extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *,
rtx, rtx, rtx, rtx);
extern const char *arm_output_memory_barrier (rtx *);
extern const char *arm_output_sync_insn (rtx, rtx *);
extern unsigned int arm_sync_loop_insns (rtx , rtx *);
extern bool arm_output_addr_const_extra (FILE *, rtx);
......
gcc/config/arm/arm.h
......@@ -126,6 +126,24 @@ enum target_cpus
/* The processor for which instructions should be scheduled. */
extern enum processor_type arm_tune;
enum arm_sync_generator_tag
{
arm_sync_generator_omn,
arm_sync_generator_omrn
};
/* Wrapper to pass around a polymorphic pointer to a sync instruction
generator and. */
struct arm_sync_generator
{
enum arm_sync_generator_tag op;
union
{
rtx (* omn) (rtx, rtx, rtx);
rtx (* omrn) (rtx, rtx, rtx, rtx);
} u;
};
typedef enum arm_cond_code
{
ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
......@@ -270,6 +288,20 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
for Thumb-2. */
#define TARGET_UNIFIED_ASM TARGET_THUMB2
/* Nonzero if this chip provides the DMB instruction. */
#define TARGET_HAVE_DMB (arm_arch7)
/* Nonzero if this chip implements a memory barrier via CP15. */
#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
/* Nonzero if this chip implements a memory barrier instruction. */
#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
/* Nonzero if this chip supports ldrex and strex */
#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
/* True iff the full BPABI is being used. If TARGET_BPABI is true,
then TARGET_AAPCS_BASED must be true -- but the converse does not
......@@ -403,6 +435,12 @@ extern int arm_arch5e;
/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
extern int arm_arch6;
/* Nonzero if this chip supports the ARM Architecture 6k extensions. */
extern int arm_arch6k;
/* Nonzero if this chip supports the ARM Architecture 7 extensions. */
extern int arm_arch7;
/* Nonzero if instructions not present in the 'M' profile can be used. */
extern int arm_arch_notm;
......
gcc/config/arm/arm.md
......@@ -103,6 +103,7 @@
(UNSPEC_RBIT 26) ; rbit operation.
(UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
; another symbolic address.
(UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
]
)
......@@ -137,6 +138,11 @@
(VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions
(VUNSPEC_EH_RETURN 20); Use to override the return address for exception
; handling.
(VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap.
(VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set.
(VUNSPEC_SYNC_OP 23) ; Represent a sync_<op>
(VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_<op>
(VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_<op>
]
)
......@@ -164,8 +170,21 @@
(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
(const (symbol_ref "arm_fpu_attr")))
(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none"))
(define_attr "sync_release_barrier" "yes,no" (const_string "yes"))
(define_attr "sync_op" "none,add,sub,ior,xor,and,nand"
(const_string "none"))
; LENGTH of an instruction (in bytes)
(define_attr "length" "" (const_int 4))
(define_attr "length" ""
(cond [(not (eq_attr "sync_memory" "none"))
(symbol_ref "arm_sync_loop_insns (insn, operands) * 4")
] (const_int 4)))
; The architecture which supports the instruction (or alternative).
; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
......@@ -10657,4 +10676,5 @@
(include "thumb2.md")
;; Neon patterns
(include "neon.md")
;; Synchronization Primitives
(include "sync.md")
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