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Commit 029435a3 by Carl Love Committed by Carl Love
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vsx.md (first_match_index_<mode>): Calculate index using natural element order. 

gcc/ChangeLog:

2018-06-04  Carl Love  <cel@us.ibm.com>

	* gcc/config/rs6000/vsx.md (first_match_index_<mode>): Calculate index
	using natural element order.  Use gen_lshrsi3 instead of gen_ashrsi3
	as it is slightly cheaper.
	(first_match_or_eos_index_<mode>):
	Calculate index using natural element order.
	(first_match_index_<mode>):
	Calculate index using natural element order.
	(first_match_or_eos_index_<mode>):
	Calculate index using natural order.
	(define_insn vclzlsbb): Change to define_insn vclzlsbb_<mode>.
	for BE and LE modes.
	* gcc/config/rs6000/rs6000-c.c: Rename P9V_BUILTIN_VCLZLSBB,
	P9V_BUILTIN_VCLZLSBB_V16QI.
	* gcc/config/rs6000/rs6000-builtin.def: Make VCLZLSBB mode
	specific.

gcc/testsuite/ChangeLog:

2018-06-04  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-8-p9-runnable.c: Add additional
	debug print statements.  Fix a few formating issues.

From-SVN: r261255
parent 20f136af
Showing with 81 additions and 20 deletions
gcc/ChangeLog
2018-06-04 Carl Love <cel@us.ibm.com>
* gcc/config/rs6000/vsx.md (first_match_index_<mode>): Calculate index
using natural element order. Use gen_lshrsi3 instead of gen_ashrsi3
as it is slightly cheaper.
(first_match_or_eos_index_<mode>):
Calculate index using natural element order.
(first_match_index_<mode>):
Calculate index using natural element order.
(first_match_or_eos_index_<mode>):
Calculate index using natural order.
(define_insn vclzlsbb): Change to define_insn vclzlsbb_<mode>.
for BE and LE modes.
* gcc/config/rs6000/rs6000-c.c: Rename P9V_BUILTIN_VCLZLSBB,
P9V_BUILTIN_VCLZLSBB_V16QI.
* gcc/config/rs6000/rs6000-builtin.def: Make VCLZLSBB mode
specific.
2018-06-06 Kelvin Nilsen <kelvin@gcc.gnu.org>
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Adjust
......
gcc/config/rs6000/rs6000-builtin.def
......@@ -2214,7 +2214,9 @@ BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC)
BU_P9V_64BIT_AV_X (XST_LEN_R, "xst_len_r", MISC)
/* 1 argument vector functions added in ISA 3.0 (power9). */
BU_P9V_AV_1 (VCLZLSBB, "vclzlsbb", CONST, vclzlsbb)
BU_P9V_AV_1 (VCLZLSBB_V16QI, "vclzlsbb_v16qi", CONST, vclzlsbb_v16qi)
BU_P9V_AV_1 (VCLZLSBB_V8HI, "vclzlsbb_v8hi", CONST, vclzlsbb_v8hi)
BU_P9V_AV_1 (VCLZLSBB_V4SI, "vclzlsbb_v4si", CONST, vclzlsbb_v4si)
BU_P9V_AV_1 (VCTZLSBB_V16QI, "vctzlsbb_v16qi", CONST, vctzlsbb_v16qi)
BU_P9V_AV_1 (VCTZLSBB_V8HI, "vctzlsbb_v8hi", CONST, vctzlsbb_v8hi)
BU_P9V_AV_1 (VCTZLSBB_V4SI, "vctzlsbb_v4si", CONST, vctzlsbb_v4si)
......
gcc/config/rs6000/rs6000-c.c
......@@ -5437,9 +5437,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
{ P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
{ P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
......
gcc/config/rs6000/vsx.md
......@@ -4723,7 +4723,8 @@
"vcmpnez<VSX_EXTRACT_WIDTH>. %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Return first position of match between vectors
;; Return first position of match between vectors using natural order
;; for both LE and BE execution modes.
(define_expand "first_match_index_<mode>"
[(match_operand:SI 0 "register_operand")
(unspec:SI [(match_operand:VSX_EXTRACT_I 1 "register_operand")
......@@ -4743,17 +4744,26 @@
sh = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) / 2;
if (<MODE>mode == V16QImode)
emit_insn (gen_vctzlsbb_<mode> (operands[0], not_result));
{
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (operands[0], not_result));
else
emit_insn (gen_vclzlsbb_<mode> (operands[0], not_result));
}
else
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_vctzlsbb_<mode> (tmp, not_result));
emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (sh)));
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (tmp, not_result));
else
emit_insn (gen_vclzlsbb_<mode> (tmp, not_result));
emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (sh)));
}
DONE;
})
;; Return first position of match between vectors or end of string (EOS)
;; Return first position of match between vectors or end of string (EOS) using
;; natural element order for both LE and BE execution modes.
(define_expand "first_match_or_eos_index_<mode>"
[(match_operand:SI 0 "register_operand")
(unspec: SI [(match_operand:VSX_EXTRACT_I 1 "register_operand")
......@@ -4785,17 +4795,26 @@
sh = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) / 2;
if (<MODE>mode == V16QImode)
emit_insn (gen_vctzlsbb_<mode> (operands[0], result));
{
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (operands[0], result));
else
emit_insn (gen_vclzlsbb_<mode> (operands[0], result));
}
else
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_vctzlsbb_<mode> (tmp, result));
emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (sh)));
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (tmp, result));
else
emit_insn (gen_vclzlsbb_<mode> (tmp, result));
emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (sh)));
}
DONE;
})
;; Return first position of mismatch between vectors
;; Return first position of mismatch between vectors using natural
;; element order for both LE and BE execution modes.
(define_expand "first_mismatch_index_<mode>"
[(match_operand:SI 0 "register_operand")
(unspec: SI [(match_operand:VSX_EXTRACT_I 1 "register_operand")
......@@ -4811,17 +4830,26 @@
sh = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) / 2;
if (<MODE>mode == V16QImode)
emit_insn (gen_vctzlsbb_<mode> (operands[0], cmp_result));
{
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (operands[0], cmp_result));
else
emit_insn (gen_vclzlsbb_<mode> (operands[0], cmp_result));
}
else
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_vctzlsbb_<mode> (tmp, cmp_result));
emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (sh)));
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (tmp, cmp_result));
else
emit_insn (gen_vclzlsbb_<mode> (tmp, cmp_result));
emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (sh)));
}
DONE;
})
;; Return first position of mismatch between vectors or end of string (EOS)
;; using natural element order for both LE and BE execution modes.
(define_expand "first_mismatch_or_eos_index_<mode>"
[(match_operand:SI 0 "register_operand")
(unspec: SI [(match_operand:VSX_EXTRACT_I 1 "register_operand")
......@@ -4856,12 +4884,20 @@
sh = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) / 2;
if (<MODE>mode == V16QImode)
emit_insn (gen_vctzlsbb_<mode> (operands[0], result));
{
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (operands[0], result));
else
emit_insn (gen_vclzlsbb_<mode> (operands[0], result));
}
else
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_vctzlsbb_<mode> (tmp, result));
emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (sh)));
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_vctzlsbb_<mode> (tmp, result));
else
emit_insn (gen_vclzlsbb_<mode> (tmp, result));
emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (sh)));
}
DONE;
})
......@@ -5040,10 +5076,10 @@
[(set_attr "type" "vecsimple")])
;; Vector Count Leading Zero Least-Significant Bits Byte
(define_insn "vclzlsbb"
(define_insn "vclzlsbb_<mode>"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:V16QI 1 "altivec_register_operand" "v")]
[(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")]
UNSPEC_VCLZLSBB))]
"TARGET_P9_VECTOR"
"vclzlsbb %0,%1"
......
gcc/testsuite/ChangeLog
2018-06-04 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-8-p9-runnable.c: Add additional
debug print statements. Fix a few formating issues.
2018-06-06 Michael Meissner <meissner@linux.ibm.com>
PR target/85657
......
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