Allow zero operand in sparc VIS3 cmask patterns.

	* config/sparc/sparc.md (cmask patterns): Allow zero operand.

From-SVN: r180715

gcc/ChangeLog

 2011-10-31  David S. Miller  <davem@davemloft.net>
 
+	* config/sparc/sparc.md (cmask patterns): Allow zero operand.
+
 	* dwarf2out.c (cached_next_real_insn): New.
 	(dwarf2out_end_epilogue): Set it to NULL_RTX.
 	(dwarf2out_var_location): Remove cached_next_real_insn local static.

gcc/config/sparc/sparc.md

@@ -8452,7 +8452,7 @@
 ;; Conditional moves are possible via fcmpX --> cmaskX -> bshuffle
 (define_insn "cmask8<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
 	            (reg:DI GSR_REG)]
                    UNSPEC_CMASK8))]
   "TARGET_VIS3"
@@ -8460,7 +8460,7 @@
 
 (define_insn "cmask16<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
 	            (reg:DI GSR_REG)]
                    UNSPEC_CMASK16))]
   "TARGET_VIS3"
@@ -8468,7 +8468,7 @@
 
 (define_insn "cmask32<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
 	            (reg:DI GSR_REG)]
                    UNSPEC_CMASK32))]
   "TARGET_VIS3"