Add AMD btver2 pipeline descriptions

From-SVN: r195319

gcc/ChangeLog

+2013-01-20  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+	btver2 pipeline descriptions.
+	* config/i386/i386.c: Enable CPU_BTVER2 to use btver2 pipeline
+	descriptions.
+	* config/i386/i386.md (btver2_decode): New type attributes.
+	* config/i386/sse.md (btver2_decode, btver2_sse_attr): New 
+	type attributes.
+	* config/i386/btver2.md: New file describing btver2 pipelines.
+
 2013-01-19  Andrew Pinski  <apinski@cavium.com>
 
 	PR tree-optimization/52631

gcc/config/i386/i386.c

@@ -1744,10 +1744,10 @@ const struct processor_costs *ix86_cost = &pentium_cost;
 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
-#define m_BDVER	(m_BDVER1 | m_BDVER2 | m_BDVER3)
-#define m_BTVER (m_BTVER1 | m_BTVER2)
 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
+#define m_BDVER	(m_BDVER1 | m_BDVER2 | m_BDVER3)
+#define m_BTVER (m_BTVER1 | m_BTVER2)
 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
 
 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
@@ -2990,7 +2990,7 @@ ix86_option_override_internal (bool main_args_p)
 	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
 	| PTA_FXSR | PTA_XSAVE},
-      {"btver2", PROCESSOR_BTVER2, CPU_GENERIC64,
+      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
 	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
 	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX

gcc/config/i386/i386.md

@@ -945,6 +945,7 @@
 (include "athlon.md")
 (include "bdver1.md")
 (include "bdver3.md")
+(include "btver2.md")
 (include "geode.md")
 (include "atom.md")
 (include "core2.md")
@@ -5058,6 +5059,7 @@
    (set_attr "athlon_decode" "double,direct")
    (set_attr "amdfam10_decode" "vector,double")
    (set_attr "bdver1_decode" "double,direct")
+   (set_attr "btver2_decode" "double,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*float<SWI48:mode><MODEF:mode>2_sse_interunit"
@@ -5079,6 +5081,7 @@
    (set_attr "athlon_decode" "double,direct")
    (set_attr "amdfam10_decode" "vector,double")
    (set_attr "bdver1_decode" "double,direct")
+   (set_attr "btver2_decode" "double,double")
    (set_attr "fp_int_src" "true")])
 
 (define_split
@@ -11979,6 +11982,7 @@
   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")
    (set_attr "prefix_rep" "1")
+   (set_attr "btver2_decode" "double")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*bsf<mode>_1"
@@ -11991,6 +11995,7 @@
   "bsf{<imodesuffix>}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")
+   (set_attr "btver2_decode" "double")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "ctz<mode>2"
@@ -12052,26 +12057,28 @@
 
 ;; BMI instructions.
 (define_insn "*bmi_andn_<mode>"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
+  [(set (match_operand:SWI48 0 "register_operand" "=r,r")
         (and:SWI48
           (not:SWI48
-            (match_operand:SWI48 1 "register_operand" "r"))
-            (match_operand:SWI48 2 "nonimmediate_operand" "rm")))
+            (match_operand:SWI48 1 "register_operand" "r,r"))
+            (match_operand:SWI48 2 "nonimmediate_operand" "r,m")))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI"
   "andn\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "bitmanip")
+   (set_attr "btver2_decode" "direct, double")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "bmi_bextr_<mode>"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-        (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
-                       (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
+  [(set (match_operand:SWI48 0 "register_operand" "=r,r")
+        (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r,r")
+                       (match_operand:SWI48 2 "nonimmediate_operand" "r,m")]
                        UNSPEC_BEXTR))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI"
   "bextr\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "bitmanip")
+   (set_attr "btver2_decode" "direct, double")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*bmi_blsi_<mode>"
@@ -12084,6 +12091,7 @@
   "TARGET_BMI"
   "blsi\t{%1, %0|%0, %1}"
   [(set_attr "type" "bitmanip")
+   (set_attr "btver2_decode" "double")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*bmi_blsmsk_<mode>"
@@ -12097,6 +12105,7 @@
   "TARGET_BMI"
   "blsmsk\t{%1, %0|%0, %1}"
   [(set_attr "type" "bitmanip")
+   (set_attr "btver2_decode" "double")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*bmi_blsr_<mode>"
@@ -12110,6 +12119,7 @@
    "TARGET_BMI"
    "blsr\t{%1, %0|%0, %1}"
   [(set_attr "type" "bitmanip")
+   (set_attr "btver2_decode" "double")
    (set_attr "mode" "<MODE>")])
 
 ;; BMI2 instructions.
@@ -13043,6 +13053,7 @@
   "%vrcpss\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
+   (set_attr "btver2_sse_attr" "rcp")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "SF")])
 
@@ -13389,6 +13400,7 @@
   "%vrsqrtss\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
+   (set_attr "btver2_sse_attr" "rcp")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "SF")])
 
@@ -13410,6 +13422,7 @@
   "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "sqrt")
+   (set_attr "btver2_sse_attr" "sqrt")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")
    (set_attr "athlon_decode" "*")