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riscv-gcc-1
Commit 00892272 by Georg-Johann Lay Committed by Georg-Johann Lay
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* Fix typos. Remove trailing blanks. Fix coding style. 

From-SVN: r195151
parent d0ad394c
Showing with 202 additions and 133 deletions
gcc/ChangeLog
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-stdint.h: Remove trailing blanks.
* config/avr/avr-log.h: Same.
* config/avr/avr-arch.h: Same.
* config/avr/avr-devices.c: Same.
* config/avr/avr-dimode.md: Same.
* config/avr/predicates.md: Same.
* config/avr/avr-c.c: Same. And fix typo.
* config/avr/avr-protos.h: Same. And:
(function_arg_regno_p): Rename to avr_function_arg_regno_p.
(init_cumulative_args): Rename to avr_init_cumulative_args.
(expand_prologue): Rename to avr_expand_prologue.
(expand_epilogue): Rename to avr_expand_epilogue.
(adjust_insn_length): Rename to avr_adjust_insn_length.
(notice_update_cc): Rename to avr_notice_update_cc.
(final_prescan_insn): Rename to avr_final_prescan_insn.
* config/avr/avr.c: Same.
* config/avr/avr.h: Same.
* config/avr/avr.md: Remove trailing blanks.
(prologue): Use avr_expand_prologue.
(epilogue, sibcall_epilogue): Use avr_expand_epilogue.
2013-01-14 Richard Biener <rguenther@suse.de>
* tree-cfg.c (verify_expr_location, verify_expr_location_1,
......
gcc/config/avr/avr-c.c
......@@ -40,7 +40,7 @@ avr_register_target_pragmas (void)
gcc_assert (ADDR_SPACE_GENERIC == ADDR_SPACE_RAM);
/* Register address spaces. The order must be the same as in the respective
enum from avr.h (or designated initialized must be used in avr.c). */
enum from avr.h (or designated initializers must be used in avr.c). */
for (i = 0; i < ADDR_SPACE_COUNT; i++)
{
......@@ -52,7 +52,7 @@ avr_register_target_pragmas (void)
}
/* Transorm LO into uppercase and write the result to UP.
/* Transform LO into uppercase and write the result to UP.
You must provide enough space for UP. Return UP. */
static char*
......@@ -151,8 +151,8 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
cpp_define (pfile, "__WITH_AVRLIBC__");
#endif /* WITH_AVRLIBC */
/* Define builtin macros so that the user can easily query if or if not
non-generic address spaces (and which) are supported.
/* Define builtin macros so that the user can easily query whether
non-generic address spaces (and which) are supported or not.
This is only supported for C. For C++, a language extension is needed
(as mentioned in ISO/IEC DTR 18037; Annex F.2) which is not
implemented in GCC up to now. */
......@@ -174,8 +174,8 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
}
}
/* Define builtin macros so that the user can easily query if or
if not a specific builtin is available. */
/* Define builtin macros so that the user can easily query whether or
not a specific builtin is available. */
for (i = 0; avr_builtin_name[i]; i++)
{
......
gcc/config/avr/avr-log.c
......@@ -281,7 +281,8 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
break;
case 'm':
fputs (GET_MODE_NAME ((enum machine_mode) va_arg (ap, int)), file);
fputs (GET_MODE_NAME ((enum machine_mode) va_arg (ap, int)),
file);
break;
case 'C':
......
gcc/config/avr/avr-protos.h
......@@ -20,11 +20,11 @@
<http://www.gnu.org/licenses/>. */
extern int function_arg_regno_p (int r);
extern int avr_function_arg_regno_p (int r);
extern void avr_cpu_cpp_builtins (struct cpp_reader * pfile);
extern enum reg_class avr_regno_reg_class (int r);
extern void asm_globalize_label (FILE *file, const char *name);
extern void order_regs_for_local_alloc (void);
extern void avr_adjust_reg_alloc_order (void);
extern int avr_initial_elimination_offset (int from, int to);
extern int avr_simple_epilogue (void);
extern int avr_hard_regno_rename_ok (unsigned int, unsigned int);
......@@ -38,8 +38,7 @@ extern void asm_output_external (FILE *file, tree decl, char *name);
extern int avr_progmem_p (tree decl, tree attributes);
#ifdef RTX_CODE /* inside TREE_CODE */
extern void init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
rtx libname, tree fndecl);
extern void avr_init_cumulative_args (CUMULATIVE_ARGS*, tree, rtx, tree);
#endif /* RTX_CODE inside TREE_CODE */
#endif /* TREE_CODE */
......@@ -78,8 +77,8 @@ extern bool avr_rotate_bytes (rtx operands[]);
extern const char* avr_out_fract (rtx, rtx[], bool, int*);
extern rtx avr_to_int_mode (rtx);
extern void expand_prologue (void);
extern void expand_epilogue (bool);
extern void avr_expand_prologue (void);
extern void avr_expand_epilogue (bool);
extern bool avr_emit_movmemhi (rtx*);
extern int avr_epilogue_uses (int regno);
extern int avr_starting_frame_offset (void);
......@@ -96,12 +95,12 @@ extern bool avr_popcount_each_byte (rtx, int, int);
extern bool avr_has_nibble_0xf (rtx);
extern int extra_constraint_Q (rtx x);
extern int adjust_insn_length (rtx insn, int len);
extern int avr_adjust_insn_length (rtx insn, int len);
extern const char* output_reload_inhi (rtx*, rtx, int*);
extern const char* output_reload_insisf (rtx*, rtx, int*);
extern const char* avr_out_reload_inpsi (rtx*, rtx, int*);
extern const char* avr_out_lpm (rtx, rtx*, int*);
extern void notice_update_cc (rtx body, rtx insn);
extern void avr_notice_update_cc (rtx body, rtx insn);
extern int reg_unused_after (rtx insn, rtx reg);
extern int _reg_unused_after (rtx insn, rtx reg);
extern int avr_jump_mode (rtx x, rtx insn);
......@@ -109,7 +108,7 @@ extern int test_hard_reg_class (enum reg_class rclass, rtx x);
extern int jump_over_one_insn_p (rtx insn, rtx dest);
extern int avr_hard_regno_mode_ok (int regno, enum machine_mode mode);
extern void final_prescan_insn (rtx insn, rtx *operand, int num_operands);
extern void avr_final_prescan_insn (rtx insn, rtx *operand, int num_operands);
extern int avr_simplify_comparison_p (enum machine_mode mode,
RTX_CODE op, rtx x);
extern RTX_CODE avr_normalize_condition (RTX_CODE condition);
......
gcc/config/avr/avr.c
......@@ -56,7 +56,7 @@
/* The 4 bits starting at SECTION_MACH_DEP are reserved to store the
address space where data is to be located.
As the only non-generic address spaces are all located in Flash,
As the only non-generic address spaces are all located in flash,
this can be used to test if data shall go into some .progmem* section.
This must be the rightmost field of machine dependent section flags. */
#define AVR_SECTION_PROGMEM (0xf * SECTION_MACH_DEP)
......@@ -97,7 +97,7 @@ const avr_addrspace_t avr_addrspace[ADDR_SPACE_COUNT] =
typedef struct
{
/* SREG: The pocessor status */
/* SREG: The processor status */
int sreg;
/* RAMPX, RAMPY, RAMPD and CCP of XMEGA */
......@@ -139,7 +139,7 @@ static struct machine_function * avr_init_machine_status (void);
/* Prototypes for hook implementors if needed before their implementation. */
static bool avr_rtx_costs (rtx, int, int, int, int *, bool);
static bool avr_rtx_costs (rtx, int, int, int, int*, bool);
/* Allocate registers from r25 to r8 for parameters for function calls. */
......@@ -276,7 +276,7 @@ avr_option_override (void)
to pseudos that cross calls and tries so save-restore them around calls
in order to reduce the number of stack slots needed.
This might leads to situations where reload is no more able to cope
This might lead to situations where reload is no more able to cope
with the challenge of AVR's very few address registers and fails to
perform the requested spills. */
......@@ -297,7 +297,7 @@ avr_option_override (void)
avr_current_device = &avr_mcu_types[avr_mcu_index];
avr_current_arch = &avr_arch_types[avr_current_device->arch];
/* RAM addresses of some SFRs common to all Devices in respective Arch. */
/* RAM addresses of some SFRs common to all devices in respective arch. */
/* SREG: Status Register containing flags like I (global IRQ) */
avr_addr.sreg = 0x3F + avr_current_arch->sfr_offset;
......@@ -356,6 +356,7 @@ avr_init_expanders (void)
}
/* Implement `REGNO_REG_CLASS'. */
/* Return register class for register R. */
enum reg_class
......@@ -406,7 +407,7 @@ avr_scalar_mode_supported_p (enum machine_mode mode)
}
/* Return TRUE if DECL is a VAR_DECL located in Flash and FALSE, otherwise. */
/* Return TRUE if DECL is a VAR_DECL located in flash and FALSE, otherwise. */
static bool
avr_decl_flash_p (tree decl)
......@@ -421,7 +422,7 @@ avr_decl_flash_p (tree decl)
}
/* Return TRUE if DECL is a VAR_DECL located in the 24-bit Flash
/* Return TRUE if DECL is a VAR_DECL located in the 24-bit flash
address space and FALSE, otherwise. */
static bool
......@@ -437,7 +438,7 @@ avr_decl_memx_p (tree decl)
}
/* Return TRUE if X is a MEM rtx located in Flash and FALSE, otherwise. */
/* Return TRUE if X is a MEM rtx located in flash and FALSE, otherwise. */
bool
avr_mem_flash_p (rtx x)
......@@ -447,7 +448,7 @@ avr_mem_flash_p (rtx x)
}
/* Return TRUE if X is a MEM rtx located in the 24-bit Flash
/* Return TRUE if X is a MEM rtx located in the 24-bit flash
address space and FALSE, otherwise. */
bool
......@@ -592,7 +593,7 @@ avr_set_current_function (tree decl)
name, isr);
}
/* Avoid the above diagnosis to be printed more than once. */
/* Don't print the above diagnostics more than once. */
cfun->machine->attributes_checked_p = 1;
}
......@@ -654,6 +655,7 @@ avr_regs_to_save (HARD_REG_SET *set)
/* No need to save any registers if the function never returns or
has the "OS_task" or "OS_main" attribute. */
if (TREE_THIS_VOLATILE (current_function_decl)
|| cfun->machine->is_OS_task
|| cfun->machine->is_OS_main)
......@@ -663,6 +665,7 @@ avr_regs_to_save (HARD_REG_SET *set)
{
/* Do not push/pop __tmp_reg__, __zero_reg__, as well as
any global register variables. */
if (fixed_regs[reg])
continue;
......@@ -705,13 +708,14 @@ avr_can_eliminate (const int from, const int to)
}
/* Implement TARGET_WARN_FUNC_RETURN. */
/* Implement `TARGET_WARN_FUNC_RETURN'. */
static bool
avr_warn_func_return (tree decl)
{
/* Naked functions are implemented entirely in assembly, including the
return sequence, so suppress warnings about this. */
return !avr_naked_function_p (decl);
}
......@@ -800,8 +804,9 @@ avr_builtin_setjmp_frame_value (void)
}
/* Return contents of MEM at frame pointer + stack size + 1 (+2 if 3 byte PC).
/* Return contents of MEM at frame pointer + stack size + 1 (+2 if 3-byte PC).
This is return address of function. */
rtx
avr_return_addr_rtx (int count, rtx tem)
{
......@@ -814,7 +819,8 @@ avr_return_addr_rtx (int count, rtx tem)
if (AVR_3_BYTE_PC)
{
r = gen_rtx_SYMBOL_REF (Pmode, ".L__stack_usage+2");
warning (0, "'builtin_return_address' contains only 2 bytes of address");
warning (0, "%<builtin_return_address%> contains only 2 bytes"
" of address");
}
else
r = gen_rtx_SYMBOL_REF (Pmode, ".L__stack_usage+1");
......@@ -846,8 +852,8 @@ static int
sequent_regs_live (void)
{
int reg;
int live_seq=0;
int cur_seq=0;
int live_seq = 0;
int cur_seq = 0;
for (reg = 0; reg < 18; ++reg)
{
......@@ -914,7 +920,8 @@ get_sequence_length (rtx insns)
return length;
}
/* Implement INCOMING_RETURN_ADDR_RTX. */
/* Implement `INCOMING_RETURN_ADDR_RTX'. */
rtx
avr_incoming_return_addr_rtx (void)
......@@ -1240,7 +1247,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set)
/* Output function prologue. */
void
expand_prologue (void)
avr_expand_prologue (void)
{
HARD_REG_SET set;
HOST_WIDE_INT size;
......@@ -1314,6 +1321,8 @@ expand_prologue (void)
current_function_static_stack_size = cfun->machine->stack_usage;
}
/* Implement `TARGET_ASM_FUNCTION_END_PROLOGUE'. */
/* Output summary at end of function prologue. */
static void
......@@ -1351,7 +1360,7 @@ avr_asm_function_end_prologue (FILE *file)
}
/* Implement EPILOGUE_USES. */
/* Implement `EPILOGUE_USES'. */
int
avr_epilogue_uses (int regno ATTRIBUTE_UNUSED)
......@@ -1363,7 +1372,7 @@ avr_epilogue_uses (int regno ATTRIBUTE_UNUSED)
return 0;
}
/* Helper for expand_epilogue. Emit a pop of a byte register. */
/* Helper for avr_expand_epilogue. Emit a pop of a byte register. */
static void
emit_pop_byte (unsigned regno)
......@@ -1380,7 +1389,7 @@ emit_pop_byte (unsigned regno)
/* Output RTL epilogue. */
void
expand_epilogue (bool sibcall_p)
avr_expand_epilogue (bool sibcall_p)
{
int reg;
int live_seq;
......@@ -1514,7 +1523,7 @@ expand_epilogue (bool sibcall_p)
if (frame_pointer_needed
&& !(cfun->machine->is_OS_task || cfun->machine->is_OS_main))
{
/* Restore previous frame_pointer. See expand_prologue for
/* Restore previous frame_pointer. See avr_expand_prologue for
rationale for not using pophi. */
emit_pop_byte (REG_Y + 1);
......@@ -1579,7 +1588,8 @@ expand_epilogue (bool sibcall_p)
emit_jump_insn (gen_return ());
}
/* Output summary messages at beginning of function epilogue. */
/* Implement `TARGET_ASM_FUNCTION_BEGIN_EPILOGUE'. */
static void
avr_asm_function_begin_epilogue (FILE *file)
......@@ -1588,7 +1598,7 @@ avr_asm_function_begin_epilogue (FILE *file)
}
/* Implement TARGET_CANNOT_MODITY_JUMPS_P */
/* Implement `TARGET_CANNOT_MODITY_JUMPS_P'. */
static bool
avr_cannot_modify_jumps_p (void)
......@@ -1928,7 +1938,7 @@ avr_asm_len (const char* tpl, rtx* operands, int* plen, int n_words)
/* Return a pointer register name as a string. */
static const char *
static const char*
ptrreg_to_str (int regno)
{
switch (regno)
......@@ -1946,7 +1956,7 @@ ptrreg_to_str (int regno)
/* Return the condition name as a string.
Used in conditional jump constructing */
static const char *
static const char*
cond_string (enum rtx_code code)
{
switch (code)
......@@ -2009,9 +2019,10 @@ avr_print_operand_address (FILE *file, rtx addr)
/* Assembler gs() will implant word address. Make offset
a byte offset inside gs() for assembler. This is
needed because the more logical (constant+gs(sym)) is not
accepted by gas. For 128K and lower devices this is ok.
For large devices it will create a Trampoline to offset
accepted by gas. For 128K and smaller devices this is ok.
For large devices it will create a trampoline to offset
from symbol which may not be what the user really wanted. */
fprintf (file, "gs(");
output_addr_const (file, XEXP (x,0));
fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC ")",
......@@ -2228,10 +2239,12 @@ avr_print_operand (FILE *file, rtx x, int code)
avr_print_operand_address (file, x);
}
/* Worker function for `NOTICE_UPDATE_CC'. */
/* Update the condition code in the INSN. */
void
notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
avr_notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
{
rtx set;
enum attr_cc cc = get_attr_cc (insn);
......@@ -2264,7 +2277,7 @@ notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
cc = (op[1] == CONST0_RTX (GET_MODE (op[0]))
&& reg_overlap_mentioned_p (op[0], zero_reg_rtx))
/* Loading zero-reg with 0 uses CLI and thus clobbers cc0. */
/* Loading zero-reg with 0 uses CLR and thus clobbers cc0. */
? CC_CLOBBER
/* Any other "r,rL" combination does not alter cc0. */
: CC_NONE;
......@@ -2353,12 +2366,12 @@ avr_jump_mode (rtx x, rtx insn)
return 2;
}
/* return an AVR condition jump commands.
/* Return an AVR condition jump commands.
X is a comparison RTX.
LEN is a number returned by avr_jump_mode function.
if REVERSE nonzero then condition code in X must be reversed. */
If REVERSE nonzero then condition code in X must be reversed. */
const char *
const char*
ret_cond_branch (rtx x, int len, int reverse)
{
RTX_CODE cond = reverse ? reverse_condition (GET_CODE (x)) : GET_CODE (x);
......@@ -2455,10 +2468,12 @@ ret_cond_branch (rtx x, int len, int reverse)
return "";
}
/* Worker function for `FINAL_PRESCAN_INSN'. */
/* Output insn cost for next insn. */
void
final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
avr_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
int num_operands ATTRIBUTE_UNUSED)
{
if (avr_log.rtx_costs)
......@@ -2484,7 +2499,7 @@ avr_simplify_comparison_p (enum machine_mode mode, RTX_CODE op, rtx x)
mode == HImode ? 0xffff :
mode == PSImode ? 0xffffff :
mode == SImode ? 0xffffffff : 0);
if (max && op && GET_CODE (x) == CONST_INT)
if (max && op && CONST_INT_P (x))
{
if (unsigned_condition (op) != op)
max >>= 1;
......@@ -2497,20 +2512,23 @@ avr_simplify_comparison_p (enum machine_mode mode, RTX_CODE op, rtx x)
}
/* Worker function for `FUNCTION_ARG_REGNO_P'. */
/* Returns nonzero if REGNO is the number of a hard
register in which function arguments are sometimes passed. */
int
function_arg_regno_p(int r)
avr_function_arg_regno_p(int r)
{
return (r >= 8 && r <= 25);
}
/* Worker function for `INIT_CUMULATIVE_ARGS'. */
/* Initializing the variable cum for the state at the beginning
of the argument list. */
void
init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname,
avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname,
tree fndecl ATTRIBUTE_UNUSED)
{
cum->nregs = 18;
......@@ -2541,6 +2559,8 @@ avr_num_arg_regs (enum machine_mode mode, const_tree type)
return (size + 1) & ~1;
}
/* Implement `TARGET_FUNCTION_ARG'. */
/* Controls whether a function argument is passed
in a register, and which register. */
......@@ -2557,6 +2577,8 @@ avr_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
return NULL_RTX;
}
/* Implement `TARGET_FUNCTION_ARG_ADVANCE'. */
/* Update the summarizer variable CUM to advance past an argument
in the argument list. */
......@@ -2655,9 +2677,7 @@ avr_function_ok_for_sibcall (tree decl_callee, tree exp_callee)
|| cfun->machine->is_signal
|| cfun->machine->is_naked
|| avr_naked_function_p (decl_callee)
/* FIXME: For OS_task and OS_main, we are over-conservative.
This is due to missing documentation of these attributes
and what they actually should do and should not do. */
/* FIXME: For OS_task and OS_main, this might be over-conservative. */
|| (avr_OS_task_function_p (decl_callee)
!= cfun->machine->is_OS_task)
|| (avr_OS_main_function_p (decl_callee)
......@@ -3014,7 +3034,7 @@ avr_out_lpm (rtx insn, rtx *op, int *plen)
if (xop[4] == xstring_e && AVR_HAVE_RAMPD)
{
/* Reset RAMPZ to 0 so that EBI devices don't read garbage from RAM */
/* Reset RAMPZ to 0 so that EBI devices don't read garbage from RAM. */
xop[0] = zero_reg_rtx;
avr_asm_len ("out %i6,%0", xop, plen, 1);
......@@ -4401,7 +4421,7 @@ compare_eq_p (rtx insn)
compare (XOP[0], XOP[1])
for an HI/SI register XOP[0] and an integer XOP[1]. Return "".
for a register XOP[0] and a compile-time constant XOP[1]. Return "".
XOP[2] is an 8-bit scratch register as needed.
PLEN == NULL: Output instructions.
......@@ -5575,7 +5595,7 @@ avr_out_ashrpsi3 (rtx insn, rtx *op, int *plen)
}
/* 32bit arithmetic shift right ((signed long)x >> i) */
/* 32-bit arithmetic shift right ((signed long)x >> i) */
const char *
ashrsi3_out (rtx insn, rtx operands[], int *len)
......@@ -5672,7 +5692,7 @@ ashrsi3_out (rtx insn, rtx operands[], int *len)
return "";
}
/* 8bit logic shift right ((unsigned char)x >> i) */
/* 8-bit logic shift right ((unsigned char)x >> i) */
const char *
lshrqi3_out (rtx insn, rtx operands[], int *len)
......@@ -5767,7 +5787,7 @@ lshrqi3_out (rtx insn, rtx operands[], int *len)
return "";
}
/* 16bit logic shift right ((unsigned short)x >> i) */
/* 16-bit logic shift right ((unsigned short)x >> i) */
const char *
lshrhi3_out (rtx insn, rtx operands[], int *len)
......@@ -6078,7 +6098,7 @@ avr_out_lshrpsi3 (rtx insn, rtx *op, int *plen)
}
/* 32bit logic shift right ((unsigned int)x >> i) */
/* 32-bit logic shift right ((unsigned int)x >> i) */
const char *
lshrsi3_out (rtx insn, rtx operands[], int *len)
......@@ -6425,7 +6445,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc,
We have to compute A = A <op> B where A is a register and
B is a register or a non-zero compile time constant CONST.
A is register class "r" if unsigned && B is REG. Otherwise, A is in "d".
B stands for the original operand $2 in INSN. In the case of B = CONST
B stands for the original operand $2 in INSN. In the case of B = CONST,
SIGN in { -1, 1 } is the sign of B. Otherwise, SIGN is 0.
CODE is the instruction flavor we use in the asm sequence to perform <op>.
......@@ -7438,11 +7458,12 @@ avr_rotate_bytes (rtx operands[])
}
/* Worker function for `ADJUST_INSN_LENGTH'. */
/* Modifies the length assigned to instruction INSN
LEN is the initially computed length of the insn. */
int
adjust_insn_length (rtx insn, int len)
avr_adjust_insn_length (rtx insn, int len)
{
rtx *op = recog_data.operand;
enum attr_adjust_len adjust_len;
......@@ -7645,6 +7666,7 @@ _reg_unused_after (rtx insn, rtx reg)
}
/* Implement `TARGET_ASM_INTEGER'. */
/* Target hook for assembling integer objects. The AVR version needs
special handling for references to certain labels. */
......@@ -7697,6 +7719,7 @@ avr_assemble_integer (rtx x, unsigned int size, int aligned_p)
}
/* Implement `TARGET_CLASS_LIKELY_SPILLED_P'. */
/* Return value is nonzero if pseudos that have been
assigned to registers of class CLASS would likely be spilled
because registers of CLASS are needed for spill registers. */
......@@ -7707,18 +7730,19 @@ avr_class_likely_spilled_p (reg_class_t c)
return (c != ALL_REGS && c != ADDW_REGS);
}
/* Valid attributes:
progmem - put data to program memory;
signal - make a function to be hardware interrupt. After function
prologue interrupts are disabled;
interrupt - make a function to be hardware interrupt. After function
prologue interrupts are enabled;
naked - don't generate function prologue/epilogue and `ret' command.
Only `progmem' attribute valid for type. */
/* Valid attributes:
progmem - Put data to program memory.
signal - Make a function to be hardware interrupt.
After function prologue interrupts remain disabled.
interrupt - Make a function to be hardware interrupt. Before function
prologue interrupts are enabled by means of SEI.
naked - Don't generate function prologue/epilogue and RET
instruction. */
/* Handle a "progmem" attribute; arguments as in
struct attribute_spec.handler. */
static tree
avr_handle_progmem_attribute (tree *node, tree name,
tree args ATTRIBUTE_UNUSED,
......@@ -8217,6 +8241,9 @@ avr_asm_named_section (const char *name, unsigned int flags, tree decl)
default_elf_asm_named_section (name, flags, decl);
}
/* Implement `TARGET_SECTION_TYPE_FLAGS'. */
static unsigned int
avr_section_type_flags (tree decl, const char *name, int reloc)
{
......@@ -8382,10 +8409,10 @@ static void
avr_file_end (void)
{
/* Output these only if there is anything in the
.data* / .rodata* / .gnu.linkonce.* resp. .bss*
.data* / .rodata* / .gnu.linkonce.* resp. .bss* or COMMON
input section(s) - some code size can be saved by not
linking in the initialization code from libgcc if resp.
sections are empty. */
sections are empty, see PR18145. */
if (avr_need_copy_data_p)
fputs (".global __do_copy_data\n", asm_out_file);
......@@ -8394,6 +8421,8 @@ avr_file_end (void)
fputs (".global __do_clear_bss\n", asm_out_file);
}
/* Worker function for `ADJUST_REG_ALLOC_ORDER'. */
/* Choose the order in which to allocate hard registers for
pseudo-registers local to a basic block.
......@@ -8402,51 +8431,42 @@ avr_file_end (void)
next register; and so on. */
void
order_regs_for_local_alloc (void)
avr_adjust_reg_alloc_order (void)
{
unsigned int i;
static const int order_0[] = {
24,25,
18,19,
20,21,
22,23,
30,31,
26,27,
28,29,
17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
0,1,
32,33,34,35
static const int order_0[] =
{
24, 25,
18, 19, 20, 21, 22, 23,
30, 31,
26, 27, 28, 29,
17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
0, 1,
32, 33, 34, 35
};
static const int order_1[] = {
18,19,
20,21,
22,23,
24,25,
30,31,
26,27,
28,29,
17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
0,1,
32,33,34,35
static const int order_1[] =
{
18, 19, 20, 21, 22, 23, 24, 25,
30, 31,
26, 27, 28, 29,
17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
0, 1,
32, 33, 34, 35
};
static const int order_2[] = {
25,24,
23,22,
21,20,
19,18,
30,31,
26,27,
28,29,
17,16,
15,14,13,12,11,10,9,8,7,6,5,4,3,2,
1,0,
32,33,34,35
static const int order_2[] =
{
25, 24, 23, 22, 21, 20, 19, 18,
30, 31,
26, 27, 28, 29,
17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
1, 0,
32, 33, 34, 35
};
const int *order = (TARGET_ORDER_1 ? order_1 :
TARGET_ORDER_2 ? order_2 :
order_0);
for (i=0; i < ARRAY_SIZE (order_0); ++i)
for (i = 0; i < ARRAY_SIZE (order_0); ++i)
reg_alloc_order[i] = order[i];
}
......@@ -9726,7 +9746,8 @@ avr_ret_register (void)
return 24;
}
/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. */
/* Implement `TARGET_FUNCTION_VALUE_REGNO_P'. */
static bool
avr_function_value_regno_p (const unsigned int regno)
......@@ -9734,6 +9755,8 @@ avr_function_value_regno_p (const unsigned int regno)
return (regno == avr_ret_register ());
}
/* Implement `TARGET_LIBCALL_VALUE'. */
/* Create an RTX representing the place where a
library function returns a value of mode MODE. */
......@@ -9749,6 +9772,8 @@ avr_libcall_value (enum machine_mode mode,
return gen_rtx_REG (mode, avr_ret_register () + 2 - offs);
}
/* Implement `TARGET_FUNCTION_VALUE'. */
/* Create an RTX representing the place where a
function returns a value of data type VALTYPE. */
......@@ -9851,6 +9876,8 @@ jump_over_one_insn_p (rtx insn, rtx dest)
&& avr_2word_insn_p (next_active_insn (insn))));
}
/* Worker function for `HARD_REGNO_MODE_OK'. */
/* Returns 1 if a value of mode MODE can be stored starting with hard
register number REGNO. On the enhanced core, anything larger than
1 byte must start in even numbered register for "movw" to work
......@@ -10303,7 +10330,7 @@ output_reload_insisf (rtx *op, rtx clobber_reg, int *len)
return "";
}
const char *
const char*
avr_out_reload_inpsi (rtx *op, rtx clobber_reg, int *len)
{
output_reload_in_const (op, clobber_reg, len, false);
......@@ -10311,6 +10338,8 @@ avr_out_reload_inpsi (rtx *op, rtx clobber_reg, int *len)
}
/* Worker function for `ASM_OUTPUT_ADDR_VEC_ELT'. */
void
avr_output_addr_vec_elt (FILE *stream, int value)
{
......@@ -10320,6 +10349,8 @@ avr_output_addr_vec_elt (FILE *stream, int value)
fprintf (stream, "\trjmp .L%d\n", value);
}
/* Implement `TARGET_HARD_REGNO_SCRATCH_OK'. */
/* Returns true if SCRATCH are safe to be allocated as a scratch
registers (for a define_peephole2) in the current function. */
......@@ -10346,6 +10377,8 @@ avr_hard_regno_scratch_ok (unsigned int regno)
return true;
}
/* Worker function for `HARD_REGNO_RENAME_OK'. */
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
int
......@@ -10382,7 +10415,7 @@ avr_hard_regno_rename_ok (unsigned int old_reg,
Operand 2: bit number.
Operand 3: label to jump to if the test is true. */
const char *
const char*
avr_out_sbxx_branch (rtx insn, rtx operands[])
{
enum rtx_code comp = GET_CODE (operands[0]);
......@@ -10442,7 +10475,7 @@ avr_out_sbxx_branch (rtx insn, rtx operands[])
return "";
}
/* Worker function for TARGET_ASM_CONSTRUCTOR. */
/* Worker function for `TARGET_ASM_CONSTRUCTOR'. */
static void
avr_asm_out_ctor (rtx symbol, int priority)
......@@ -10451,7 +10484,8 @@ avr_asm_out_ctor (rtx symbol, int priority)
default_ctor_section_asm_out_constructor (symbol, priority);
}
/* Worker function for TARGET_ASM_DESTRUCTOR. */
/* Worker function for `TARGET_ASM_DESTRUCTOR'. */
static void
avr_asm_out_dtor (rtx symbol, int priority)
......@@ -10460,7 +10494,8 @@ avr_asm_out_dtor (rtx symbol, int priority)
default_dtor_section_asm_out_destructor (symbol, priority);
}
/* Worker function for TARGET_RETURN_IN_MEMORY. */
/* Worker function for `TARGET_RETURN_IN_MEMORY'. */
static bool
avr_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
......@@ -11333,7 +11368,6 @@ avr_out_insert_bits (rtx *op, int *plen)
enum avr_builtin_id
{
#define DEF_BUILTIN(NAME, N_ARGS, ID, TYPE, CODE) ID,
#include "builtins.def"
#undef DEF_BUILTIN
......
gcc/config/avr/avr.h
......@@ -201,10 +201,11 @@ enum
32,33,34,35 \
}
#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
#define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order()
#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE)
......@@ -318,15 +319,19 @@ enum reg_class {
for POST_DEC targets (PR27386). */
/*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/
typedef struct avr_args {
int nregs; /* # registers available for passing */
int regno; /* next available register number */
typedef struct avr_args
{
/* # Registers available for passing */
int nregs;
/* Next available register number */
int regno;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
avr_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
#define FUNCTION_ARG_REGNO_P(r) function_arg_regno_p(r)
#define FUNCTION_ARG_REGNO_P(r) avr_function_arg_regno_p(r)
#define DEFAULT_PCC_STRUCT_RETURN 0
......@@ -415,7 +420,8 @@ typedef struct avr_args {
"r24","r25","r26","r27","r28","r29","r30","r31", \
"__SP_L__","__SP_H__","argL","argH"}
#define FINAL_PRESCAN_INSN(insn, operand, nop) final_prescan_insn (insn, operand,nop)
#define FINAL_PRESCAN_INSN(insn, operand, nop) \
avr_final_prescan_insn (insn, operand,nop)
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
{ \
......@@ -430,7 +436,7 @@ typedef struct avr_args {
}
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
avr_output_addr_vec_elt(STREAM, VALUE)
avr_output_addr_vec_elt (STREAM, VALUE)
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
do { \
......@@ -459,7 +465,7 @@ typedef struct avr_args {
after execution of an instruction whose pattern is EXP.
Do not alter them if the instruction would not alter the cc's. */
#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
#define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN)
/* The add insns don't set overflow in a usable way. */
#define CC_OVERFLOW_UNUSABLE 01000
......@@ -477,8 +483,8 @@ typedef struct avr_args {
#define FUNCTION_PROFILER(FILE, LABELNO) \
fprintf (FILE, "/* profiler %d */", (LABELNO))
#define ADJUST_INSN_LENGTH(INSN, LENGTH) (LENGTH =\
adjust_insn_length (INSN, LENGTH))
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
(LENGTH = avr_adjust_insn_length (INSN, LENGTH))
extern const char *avr_device_to_arch (int argc, const char **argv);
extern const char *avr_device_to_data_start (int argc, const char **argv);
......
gcc/config/avr/avr.md
......@@ -5471,7 +5471,7 @@
[(const_int 0)]
""
{
expand_prologue ();
avr_expand_prologue ();
DONE;
})
......@@ -5479,7 +5479,7 @@
[(const_int 0)]
""
{
expand_epilogue (false /* sibcall_p */);
avr_expand_epilogue (false /* sibcall_p */);
DONE;
})
......@@ -5487,7 +5487,7 @@
[(const_int 0)]
""
{
expand_epilogue (true /* sibcall_p */);
avr_expand_epilogue (true /* sibcall_p */);
DONE;
})
......
libgcc/ChangeLog
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
* config/avr/lib1funcs.S: Remove trailing blanks.
* config/avr/lib1funcs-fixed.S: Ditto.
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-lib.h: Add GPL copyright notice.
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
......
libgcc/config/avr/lib1funcs-fixed.S
/* -*- Mode: Asm -*- */
;; Copyright (C) 2012
;; Copyright (C) 2012-2013
;; Free Software Foundation, Inc.
;; Contributed by Sean D'Epagnier (sean@depagnier.com)
;; Georg-Johann Lay (avr@gjlay.de)
......
libgcc/config/avr/lib1funcs.S
/* -*- Mode: Asm -*- */
/* Copyright (C) 1998, 1999, 2000, 2007, 2008, 2009
/* Copyright (C) 1998-2013
Free Software Foundation, Inc.
Contributed by Denis Chertykov <chertykov@gmail.com>
......
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