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riscv-gcc-1
Commit 00892272 by Georg-Johann Lay Committed by Georg-Johann Lay
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* Fix typos. Remove trailing blanks. Fix coding style. 

From-SVN: r195151
parent d0ad394c
Showing with 183 additions and 148 deletions
gcc/ChangeLog
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-stdint.h: Remove trailing blanks.
* config/avr/avr-log.h: Same.
* config/avr/avr-arch.h: Same.
* config/avr/avr-devices.c: Same.
* config/avr/avr-dimode.md: Same.
* config/avr/predicates.md: Same.
* config/avr/avr-c.c: Same. And fix typo.
* config/avr/avr-protos.h: Same. And:
(function_arg_regno_p): Rename to avr_function_arg_regno_p.
(init_cumulative_args): Rename to avr_init_cumulative_args.
(expand_prologue): Rename to avr_expand_prologue.
(expand_epilogue): Rename to avr_expand_epilogue.
(adjust_insn_length): Rename to avr_adjust_insn_length.
(notice_update_cc): Rename to avr_notice_update_cc.
(final_prescan_insn): Rename to avr_final_prescan_insn.
* config/avr/avr.c: Same.
* config/avr/avr.h: Same.
* config/avr/avr.md: Remove trailing blanks.
(prologue): Use avr_expand_prologue.
(epilogue, sibcall_epilogue): Use avr_expand_epilogue.
2013-01-14 Richard Biener <rguenther@suse.de>
* tree-cfg.c (verify_expr_location, verify_expr_location_1,
......
gcc/config/avr/avr-arch.h
......@@ -74,7 +74,7 @@ struct base_arch_s
/* This core has the RAMPD special function register
and thus also the RAMPX, RAMPY and RAMPZ registers. */
int have_rampd;
/* Default start of data section address for architecture. */
int default_data_section_start;
......@@ -84,9 +84,9 @@ struct base_arch_s
/* Architecture id to built-in define __AVR_ARCH__ (NULL -> no macro) */
const char *const macro;
/* Architecture name. */
const char *const arch_name;
const char *const arch_name;
};
......@@ -96,16 +96,16 @@ struct mcu_type_s
{
/* Device name. */
const char *const name;
/* Index in avr_arch_types[]. */
enum avr_arch arch;
enum avr_arch arch;
/* Must lie outside user's namespace. NULL == no macro. */
const char *const macro;
/* Stack pointer have 8 bits width. */
int short_sp;
/* Some AVR devices have a core erratum when skipping a 2-word instruction.
Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE.
Problems will occur with return address is IRQ executes during the
......@@ -125,15 +125,15 @@ struct mcu_type_s
/* Core Erratum: Must not skip 2-word instruction. */
int errata_skip;
/* Start of data section. */
int data_section_start;
/* Number of 64k segments in the flash. */
int n_flash;
/* Name of device library. */
const char *const library_name;
const char *const library_name;
};
/* Map architecture to its texinfo string. */
......
gcc/config/avr/avr-c.c
......@@ -40,7 +40,7 @@ avr_register_target_pragmas (void)
gcc_assert (ADDR_SPACE_GENERIC == ADDR_SPACE_RAM);
/* Register address spaces. The order must be the same as in the respective
enum from avr.h (or designated initialized must be used in avr.c). */
enum from avr.h (or designated initializers must be used in avr.c). */
for (i = 0; i < ADDR_SPACE_COUNT; i++)
{
......@@ -52,14 +52,14 @@ avr_register_target_pragmas (void)
}
/* Transorm LO into uppercase and write the result to UP.
/* Transform LO into uppercase and write the result to UP.
You must provide enough space for UP. Return UP. */
static char*
avr_toupper (char *up, const char *lo)
{
char *up0 = up;
for (; *lo; lo++, up++)
*up = TOUPPER (*lo);
......@@ -67,7 +67,7 @@ avr_toupper (char *up, const char *lo)
return up0;
}
/* Worker function for TARGET_CPU_CPP_BUILTINS. */
static const char *const avr_builtin_name[] =
......@@ -82,7 +82,7 @@ void
avr_cpu_cpp_builtins (struct cpp_reader *pfile)
{
int i;
builtin_define_std ("AVR");
if (avr_current_arch->macro)
......@@ -139,24 +139,24 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
if (avr_current_device->errata_skip)
{
cpp_define (pfile, "__AVR_ERRATA_SKIP__");
if (avr_current_arch->have_jmp_call)
cpp_define (pfile, "__AVR_ERRATA_SKIP_JMP_CALL__");
}
cpp_define_formatted (pfile, "__AVR_SFR_OFFSET__=0x%x",
avr_current_arch->sfr_offset);
#ifdef WITH_AVRLIBC
cpp_define (pfile, "__WITH_AVRLIBC__");
#endif /* WITH_AVRLIBC */
/* Define builtin macros so that the user can easily query if or if not
non-generic address spaces (and which) are supported.
/* Define builtin macros so that the user can easily query whether
non-generic address spaces (and which) are supported or not.
This is only supported for C. For C++, a language extension is needed
(as mentioned in ISO/IEC DTR 18037; Annex F.2) which is not
implemented in GCC up to now. */
if (!strcmp (lang_hooks.name, "GNU C"))
{
for (i = 0; i < ADDR_SPACE_COUNT; i++)
......@@ -174,8 +174,8 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile)
}
}
/* Define builtin macros so that the user can easily query if or
if not a specific builtin is available. */
/* Define builtin macros so that the user can easily query whether or
not a specific builtin is available. */
for (i = 0; avr_builtin_name[i]; i++)
{
......
gcc/config/avr/avr-devices.c
......@@ -35,7 +35,7 @@ avr_arch_types[] =
/*
A M J LM E E E X R d S S O A
S U M PO L L I M A a t F ff r
M L P MV P P J E M t a R s c
M L P MV P P J E M t a R s c
XW M M M G P a r e h
X P A D t t ID */
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 32, "1", "avr1" },
......
gcc/config/avr/avr-dimode.md
......@@ -31,7 +31,7 @@
;; The DImode insns are all straight forward -- except movdi. The approach
;; of this implementation is to provide DImode insns without the burden of
;; introducing movdi.
;;
;;
;; The caveat is that if there are insns for some mode, there must also be a
;; respective move insn that describes reloads. Therefore, this
;; implementation uses an accumulator-based model with two hard-coded,
......@@ -75,7 +75,7 @@
{
emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
emit_insn (gen_adddi3_const8_insn ());
}
}
else if (const_operand (operands[2], GET_MODE (operands[2])))
{
emit_insn (gen_add<mode>3_const_insn (operands[2]));
......@@ -344,7 +344,7 @@
{
emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
emit_insn (gen_compare_const8_di2 ());
}
}
else if (const_operand (operands[2], GET_MODE (operands[2])))
{
emit_insn (gen_compare_const_<mode>2 (operands[2]));
......
gcc/config/avr/avr-log.c
......@@ -41,8 +41,8 @@
avr_edump (fmt, ...) is a shortcut for avr_fdump (stderr, fmt, ...)
== known %-codes ==
b: bool
b: bool
r: rtx
t: tree
T: tree (brief)
......@@ -55,7 +55,7 @@
H: location_t
== no arguments ==
A: call abort()
f: current_function_name()
F: caller (via __FUNCTION__)
......@@ -65,7 +65,7 @@
else return.
== same as printf ==
%: %
c: char
s: string
......@@ -95,11 +95,11 @@ static int
avr_log_fdump_e (const char *fmt, ...)
{
va_list ap;
va_start (ap, fmt);
avr_log_vadump (stderr, fmt, ap);
va_end (ap);
return 1;
}
......@@ -107,12 +107,12 @@ static int
avr_log_fdump_f (FILE *stream, const char *fmt, ...)
{
va_list ap;
va_start (ap, fmt);
if (stream)
avr_log_vadump (stream, fmt, ap);
va_end (ap);
return 1;
}
......@@ -124,7 +124,7 @@ avr_log_set_caller_e (const char *caller)
)(const char*, ...)
{
avr_log_caller = caller;
return avr_log_fdump_e;
}
......@@ -192,19 +192,19 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
default:
fputc (*(fmt-1), file);
break;
case '\\':
bs[1] = *fmt++;
fputs (bs, file);
break;
case '%':
switch (*fmt++)
{
case '%':
fputc ('%', file);
break;
case 't':
{
tree t = va_arg (ap, tree);
......@@ -222,15 +222,15 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
}
break;
}
case 'T':
print_node_brief (file, "", va_arg (ap, tree), 3);
break;
case 'd':
fprintf (file, "%d", va_arg (ap, int));
break;
case 'D':
dump_double_int (file, va_arg (ap, double_int), false);
break;
......@@ -238,23 +238,23 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
case 'X':
avr_dump_double_int_hex (file, va_arg (ap, double_int));
break;
case 'x':
fprintf (file, "%x", va_arg (ap, int));
break;
case 'b':
fprintf (file, "%s", va_arg (ap, int) ? "true" : "false");
break;
case 'c':
fputc (va_arg (ap, int), file);
break;
case 'r':
print_inline_rtx (file, va_arg (ap, rtx), 0);
break;
case 'L':
{
rtx insn = va_arg (ap, rtx);
......@@ -267,39 +267,40 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
}
break;
}
case 'f':
if (cfun && cfun->decl)
fputs (current_function_name(), file);
break;
case 's':
{
const char *str = va_arg (ap, char*);
fputs (str ? str : "(null)", file);
}
break;
case 'm':
fputs (GET_MODE_NAME ((enum machine_mode) va_arg (ap, int)), file);
fputs (GET_MODE_NAME ((enum machine_mode) va_arg (ap, int)),
file);
break;
case 'C':
fputs (rtx_name[va_arg (ap, int)], file);
break;
case 'R':
fputs (reg_class_names[va_arg (ap, int)], file);
break;
case 'F':
fputs (avr_log_caller, file);
break;
case 'H':
{
location_t loc = va_arg (ap, location_t);
if (BUILTINS_LOCATION == loc)
fprintf (file, "<BUILTIN-LOCATION>");
else if (UNKNOWN_LOCATION == loc)
......@@ -307,45 +308,45 @@ avr_log_vadump (FILE *file, const char *fmt, va_list ap)
else
fprintf (file, "%s:%d",
LOCATION_FILE (loc), LOCATION_LINE (loc));
break;
}
case '!':
if (!current_pass)
return;
/* FALLTHRU */
case '?':
avr_log_fdump_f (file, "%F[%f:%P]");
break;
case 'P':
if (current_pass)
fprintf (file, "%s(%d)",
fprintf (file, "%s(%d)",
current_pass->name,
current_pass->static_pass_number);
else
fprintf (file, "pass=?");
break;
case 'A':
fflush (file);
abort();
default:
/* Unknown %-code: Stop printing */
fprintf (file, "??? %%%c ???%s\n", *(fmt-1), fmt);
fmt = "";
break;
}
break; /* % */
}
}
fflush (file);
}
......@@ -357,14 +358,14 @@ void
avr_log_set_avr_log (void)
{
bool all = TARGET_ALL_DEBUG != 0;
if (all || avr_log_details)
{
/* Adding , at beginning and end of string makes searching easier. */
char *str = (char*) alloca (3 + strlen (avr_log_details));
bool info;
str[0] = ',';
strcat (stpcpy (str+1, avr_log_details), ",");
......
gcc/config/avr/avr-protos.h
......@@ -20,11 +20,11 @@
<http://www.gnu.org/licenses/>. */
extern int function_arg_regno_p (int r);
extern int avr_function_arg_regno_p (int r);
extern void avr_cpu_cpp_builtins (struct cpp_reader * pfile);
extern enum reg_class avr_regno_reg_class (int r);
extern void asm_globalize_label (FILE *file, const char *name);
extern void order_regs_for_local_alloc (void);
extern void avr_adjust_reg_alloc_order (void);
extern int avr_initial_elimination_offset (int from, int to);
extern int avr_simple_epilogue (void);
extern int avr_hard_regno_rename_ok (unsigned int, unsigned int);
......@@ -38,8 +38,7 @@ extern void asm_output_external (FILE *file, tree decl, char *name);
extern int avr_progmem_p (tree decl, tree attributes);
#ifdef RTX_CODE /* inside TREE_CODE */
extern void init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
rtx libname, tree fndecl);
extern void avr_init_cumulative_args (CUMULATIVE_ARGS*, tree, rtx, tree);
#endif /* RTX_CODE inside TREE_CODE */
#endif /* TREE_CODE */
......@@ -78,8 +77,8 @@ extern bool avr_rotate_bytes (rtx operands[]);
extern const char* avr_out_fract (rtx, rtx[], bool, int*);
extern rtx avr_to_int_mode (rtx);
extern void expand_prologue (void);
extern void expand_epilogue (bool);
extern void avr_expand_prologue (void);
extern void avr_expand_epilogue (bool);
extern bool avr_emit_movmemhi (rtx*);
extern int avr_epilogue_uses (int regno);
extern int avr_starting_frame_offset (void);
......@@ -96,12 +95,12 @@ extern bool avr_popcount_each_byte (rtx, int, int);
extern bool avr_has_nibble_0xf (rtx);
extern int extra_constraint_Q (rtx x);
extern int adjust_insn_length (rtx insn, int len);
extern int avr_adjust_insn_length (rtx insn, int len);
extern const char* output_reload_inhi (rtx*, rtx, int*);
extern const char* output_reload_insisf (rtx*, rtx, int*);
extern const char* avr_out_reload_inpsi (rtx*, rtx, int*);
extern const char* avr_out_lpm (rtx, rtx*, int*);
extern void notice_update_cc (rtx body, rtx insn);
extern void avr_notice_update_cc (rtx body, rtx insn);
extern int reg_unused_after (rtx insn, rtx reg);
extern int _reg_unused_after (rtx insn, rtx reg);
extern int avr_jump_mode (rtx x, rtx insn);
......@@ -109,7 +108,7 @@ extern int test_hard_reg_class (enum reg_class rclass, rtx x);
extern int jump_over_one_insn_p (rtx insn, rtx dest);
extern int avr_hard_regno_mode_ok (int regno, enum machine_mode mode);
extern void final_prescan_insn (rtx insn, rtx *operand, int num_operands);
extern void avr_final_prescan_insn (rtx insn, rtx *operand, int num_operands);
extern int avr_simplify_comparison_p (enum machine_mode mode,
RTX_CODE op, rtx x);
extern RTX_CODE avr_normalize_condition (RTX_CODE condition);
......
gcc/config/avr/avr-stdint.h
......@@ -30,7 +30,7 @@ along with GCC; see the file COPYING3. If not see
- For the same reason, [u]int_fast8_t is defined as 8-bit type.
*/
#define SIG_ATOMIC_TYPE "char"
#define INT8_TYPE "signed char"
......
gcc/config/avr/avr.c
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/avr/avr.h
......@@ -201,10 +201,11 @@ enum
32,33,34,35 \
}
#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
#define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order()
#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) avr_hard_regno_mode_ok(REGNO, MODE)
......@@ -318,15 +319,19 @@ enum reg_class {
for POST_DEC targets (PR27386). */
/*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/
typedef struct avr_args {
int nregs; /* # registers available for passing */
int regno; /* next available register number */
typedef struct avr_args
{
/* # Registers available for passing */
int nregs;
/* Next available register number */
int regno;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
avr_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
#define FUNCTION_ARG_REGNO_P(r) function_arg_regno_p(r)
#define FUNCTION_ARG_REGNO_P(r) avr_function_arg_regno_p(r)
#define DEFAULT_PCC_STRUCT_RETURN 0
......@@ -415,7 +420,8 @@ typedef struct avr_args {
"r24","r25","r26","r27","r28","r29","r30","r31", \
"__SP_L__","__SP_H__","argL","argH"}
#define FINAL_PRESCAN_INSN(insn, operand, nop) final_prescan_insn (insn, operand,nop)
#define FINAL_PRESCAN_INSN(insn, operand, nop) \
avr_final_prescan_insn (insn, operand,nop)
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
{ \
......@@ -429,8 +435,8 @@ typedef struct avr_args {
fprintf (STREAM, "\tpop\tr%d", REGNO); \
}
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
avr_output_addr_vec_elt(STREAM, VALUE)
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
avr_output_addr_vec_elt (STREAM, VALUE)
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
do { \
......@@ -459,7 +465,7 @@ typedef struct avr_args {
after execution of an instruction whose pattern is EXP.
Do not alter them if the instruction would not alter the cc's. */
#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
#define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN)
/* The add insns don't set overflow in a usable way. */
#define CC_OVERFLOW_UNUSABLE 01000
......@@ -477,8 +483,8 @@ typedef struct avr_args {
#define FUNCTION_PROFILER(FILE, LABELNO) \
fprintf (FILE, "/* profiler %d */", (LABELNO))
#define ADJUST_INSN_LENGTH(INSN, LENGTH) (LENGTH =\
adjust_insn_length (INSN, LENGTH))
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
(LENGTH = avr_adjust_insn_length (INSN, LENGTH))
extern const char *avr_device_to_arch (int argc, const char **argv);
extern const char *avr_device_to_data_start (int argc, const char **argv);
......
gcc/config/avr/predicates.md
......@@ -162,11 +162,11 @@
;; True for EQ & NE
(define_predicate "eqne_operator"
(match_code "eq,ne"))
;; True for GE & LT
(define_predicate "gelt_operator"
(match_code "ge,lt"))
;; True for GT, GTU, LE & LEU
(define_predicate "difficult_comparison_operator"
(match_code "gt,gtu,le,leu"))
......
libgcc/ChangeLog
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
* config/avr/lib1funcs.S: Remove trailing blanks.
* config/avr/lib1funcs-fixed.S: Ditto.
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-lib.h: Add GPL copyright notice.
2013-01-14 Georg-Johann Lay <avr@gjlay.de>
......
libgcc/config/avr/lib1funcs-fixed.S
/* -*- Mode: Asm -*- */
;; Copyright (C) 2012
;; Copyright (C) 2012-2013
;; Free Software Foundation, Inc.
;; Contributed by Sean D'Epagnier (sean@depagnier.com)
;; Georg-Johann Lay (avr@gjlay.de)
......@@ -163,7 +163,7 @@ ENDF __fractusasf
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Conversions from float
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
#if defined (L_fractsfqq)
DEFUN __fractsfqq
;; Multiply with 2^{24+7} to get a QQ result in r25
......@@ -408,14 +408,14 @@ DEFUN __mulusa3_round
mul A1, B0 $ add C3, r0 $ adc C0, r1
mul A0, B1 $ add C3, r0 $ adc C0, r1 $ rol C1
;; Round if T = 1. Store guarding bits outside the result for rounding
;; and left-shift by the signed version (function below).
brtc 0f
sbrc C3, 7
adiw C0, 1
0: push C3
;; The following MULs don't have LSBs outside the result.
;; C2/C3 is the high part.
......@@ -429,11 +429,11 @@ DEFUN __mulusa3_round
mul A2, B1 $ add C1, r0 $ adc C2, r1 $ sbci C3, 0
mul A3, B0 $ add C1, r0 $ adc C2, r1 $ sbci C3, 0
neg C3
mul A1, B3 $ add C2, r0 $ adc C3, r1
mul A2, B2 $ add C2, r0 $ adc C3, r1
mul A3, B1 $ add C2, r0 $ adc C3, r1
mul A2, B3 $ add C3, r0
mul A3, B2 $ add C3, r0
......@@ -636,7 +636,7 @@ DEFUN __mulusa3_round
adc C1, __zero_reg__
adc C2, __zero_reg__
adc C3, __zero_reg__
6:
6:
pop GUARD
;; Epilogue
pop CC3
......
libgcc/config/avr/lib1funcs.S
/* -*- Mode: Asm -*- */
/* Copyright (C) 1998, 1999, 2000, 2007, 2008, 2009
/* Copyright (C) 1998-2013
Free Software Foundation, Inc.
Contributed by Denis Chertykov <chertykov@gmail.com>
......@@ -151,16 +151,16 @@ __mulqi3_loop:
add r_res,r_arg2
add r_arg2,r_arg2 ; shift multiplicand
breq __mulqi3_exit ; while multiplicand != 0
lsr r_arg1 ;
lsr r_arg1 ;
brne __mulqi3_loop ; exit if multiplier = 0
__mulqi3_exit:
mov r_arg1,r_res ; result to return register
ret
ENDF __mulqi3
#undef r_arg2
#undef r_arg1
#undef r_res
#undef r_arg2
#undef r_arg1
#undef r_res
#endif /* defined (L_mulqi3) */
......@@ -370,7 +370,7 @@ DEFUN __mulsi3_helper
2: ;; B <<= 1
lsl B0 $ rol B1 $ rol B2 $ rol B3
3: ;; A >>= 1: Carry = n-th bit of A
lsr A3 $ ror A2 $ ror A1 $ ror A0
......@@ -409,7 +409,7 @@ ENDF __mulsi3_helper
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
#if defined (__AVR_HAVE_MUL__)
#if defined (__AVR_HAVE_MUL__)
#define A0 26
#define B0 18
#define C0 22
......@@ -427,7 +427,7 @@ ENDF __mulsi3_helper
/*******************************************************
Widening Multiplication 32 = 16 x 16 with MUL
*******************************************************/
#if defined (L_mulhisi3)
;;; R25:R22 = (signed long) R27:R26 * (signed long) R19:R18
;;; C3:C0 = (signed long) A1:A0 * (signed long) B1:B0
......@@ -512,7 +512,7 @@ DEFUN __mulshisi3
XJMP __muluhisi3
;; FALLTHRU
ENDF __mulshisi3
;;; R25:R22 = (one-extended long) R27:R26 * R21:R18
;;; (C3:C0) = (one-extended long) A1:A0 * B3:B0
;;; Clobbers: __tmp_reg__
......@@ -647,23 +647,23 @@ DEFUN __mulpsi3
;; C[] = 0
clr __tmp_reg__
clr C2
0: ;; Shift N-th Bit of B[] into Carry. N = 24 - Loop
LSR B2 $ ror B1 $ ror B0
;; If the N-th Bit of B[] was set...
brcc 1f
;; ...then add A[] * 2^N to the Result C[]
ADD C0,A0 $ adc C1,A1 $ adc C2,A2
1: ;; Multiply A[] by 2
LSL A0 $ rol A1 $ rol A2
;; Loop until B[] is 0
subi B0,0 $ sbci B1,0 $ sbci B2,0
brne 0b
;; Copy C[] to the return Register A[]
wmov A0, C0
mov A2, C2
......@@ -1002,7 +1002,7 @@ __udivmodqi4_ep:
rol r_arg1 ; shift dividend (with CARRY)
dec r_cnt ; decrement loop counter
brne __udivmodqi4_loop
com r_arg1 ; complement result
com r_arg1 ; complement result
; because C flag was complemented in loop
ret
ENDF __udivmodqi4
......@@ -1112,14 +1112,14 @@ __divmodhi4_exit:
ENDF __divmodhi4
#endif /* defined (L_divmodhi4) */
#undef r_remH
#undef r_remL
#undef r_arg1H
#undef r_arg1L
#undef r_arg2H
#undef r_arg2L
#undef r_remH
#undef r_remL
#undef r_arg1H
#undef r_arg1L
#undef r_arg2H
#undef r_arg2L
#undef r_cnt
......@@ -1501,8 +1501,8 @@ DEFUN __udivmod64
1: ;; Compare shifted Devidend against Divisor
;; If -- even after Shifting -- it is smaller...
CP A7,B0 $ cpc C0,B1 $ cpc C1,B2 $ cpc C2,B3
cpc C3,B4 $ cpc C4,B5 $ cpc C5,B6 $ cpc C6,B7
CP A7,B0 $ cpc C0,B1 $ cpc C1,B2 $ cpc C2,B3
cpc C3,B4 $ cpc C4,B5 $ cpc C5,B6 $ cpc C6,B7
brcc 2f
;; ...then we can subtract it. Thus, it is legal to shift left
......@@ -1596,7 +1596,7 @@ DEFUN __udivmod64
ENDF __udivmod64
#endif /* L_udivmod64 */
#if defined (L_divdi3)
......@@ -1622,7 +1622,7 @@ DEFUN __divdi3_moddi3
brmi 0f
;; Both Signs are 0: the following Complexitiy is not needed
XJMP __udivdi3_umoddi3
#endif /* SPEED_DIV */
#endif /* SPEED_DIV */
0: ;; The Prologue
;; Save 12 Registers: Y, 17...8
......@@ -1645,7 +1645,7 @@ DEFUN __divdi3_moddi3
#else
brpl 21f
#endif /* SPEED_DIV */
XCALL __negdi2
;; Adjust Divisor's Sign and SS.7 as needed
......@@ -1809,7 +1809,7 @@ ENDF __negdi2
.section .text.libgcc.prologue, "ax", @progbits
/**********************************
* This is a prologue subroutine
**********************************/
......@@ -1944,7 +1944,7 @@ _cleanup:
.section .text.libgcc, "ax", @progbits
#ifdef L_tablejump
DEFUN __tablejump2__
lsl r30
......@@ -2146,7 +2146,7 @@ ENDF __do_global_dtors
#endif /* L_dtors */
.section .text.libgcc, "ax", @progbits
#ifdef L_tablejump_elpm
DEFUN __tablejump_elpm__
#if defined (__AVR_HAVE_ELPMX__)
......@@ -2484,7 +2484,7 @@ DEFUN __loop_ffsqi2
brcc __loop_ffsqi2
mov r24, r26
clr r25
ret
ret
ENDF __loop_ffsqi2
#endif /* defined (L_loop_ffsqi2) */
......@@ -2586,7 +2586,7 @@ ENDF __clzhi2
/**********************************
* Parity
* Parity
**********************************/
#if defined (L_paritydi2)
......@@ -2702,20 +2702,20 @@ ENDF __popcountdi2
DEFUN __popcountqi2
mov __tmp_reg__, r24
andi r24, 1
lsr __tmp_reg__
lsr __tmp_reg__
lsr __tmp_reg__
lsr __tmp_reg__
adc r24, __zero_reg__
lsr __tmp_reg__
lsr __tmp_reg__
adc r24, __zero_reg__
lsr __tmp_reg__
lsr __tmp_reg__
adc r24, __zero_reg__
lsr __tmp_reg__
lsr __tmp_reg__
adc r24, __zero_reg__
lsr __tmp_reg__
lsr __tmp_reg__
adc r24, __zero_reg__
lsr __tmp_reg__
adc r24, __tmp_reg__
ret
lsr __tmp_reg__
adc r24, __tmp_reg__
ret
ENDF __popcountqi2
#endif /* defined (L_popcountqi2) */
......@@ -2850,10 +2850,10 @@ ENDF __rotldi3
.section .text.libgcc.fmul, "ax", @progbits
/***********************************************************/
/***********************************************************/
;;; Softmul versions of FMUL, FMULS and FMULSU to implement
;;; __builtin_avr_fmul* if !AVR_HAVE_MUL
/***********************************************************/
/***********************************************************/
#define A1 24
#define B1 25
......
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