Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
0081a354
Commit
0081a354
authored
Apr 16, 1994
by
Richard Kenner
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add missing blank lines.
From-SVN: r7054
parent
0d920bbf
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
7 additions
and
0 deletions
+7
-0
gcc/config/rs6000/rs6000.md
+7
-0
No files found.
gcc/config/rs6000/rs6000.md
View file @
0081a354
...
@@ -937,6 +937,7 @@
...
@@ -937,6 +937,7 @@
}
}
else
else
FAIL;
FAIL;
if (GET_CODE (operands
[
2
]
) != CONST_INT || INTVAL (operands
[
2
]
) < 0)
if (GET_CODE (operands
[
2
]
) != CONST_INT || INTVAL (operands
[
2
]
) < 0)
{
{
operands
[
2
]
= force_reg (SImode, operands
[
2
]
);
operands
[
2
]
= force_reg (SImode, operands
[
2
]
);
...
@@ -954,6 +955,7 @@
...
@@ -954,6 +955,7 @@
DONE;
DONE;
}")
}")
;; AIX architecture-independent common-mode multiply (DImode),
;; AIX architecture-independent common-mode multiply (DImode),
;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
;; R4; results in R3 and somtimes R4; link register always clobbered by bla
;; R4; results in R3 and somtimes R4; link register always clobbered by bla
...
@@ -968,6 +970,7 @@
...
@@ -968,6 +970,7 @@
(clobber (match_scratch:SI 0 "=l"))]
(clobber (match_scratch:SI 0 "=l"))]
"! TARGET_POWER && ! TARGET_POWERPC"
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mulh")
"bla __mulh")
(define_insn "mull_call"
(define_insn "mull_call"
[
(set (reg:DI 3)
[
(set (reg:DI 3)
(mult:DI (sign_extend:DI (reg:SI 3))
(mult:DI (sign_extend:DI (reg:SI 3))
...
@@ -976,6 +979,7 @@
...
@@ -976,6 +979,7 @@
(clobber (reg:SI 0))]
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __mull")
"bla __mull")
(define_insn "divss_call"
(define_insn "divss_call"
[
(set (reg:SI 3)
[
(set (reg:SI 3)
(div:SI (reg:SI 3) (reg:SI 4)))
(div:SI (reg:SI 3) (reg:SI 4)))
...
@@ -985,6 +989,7 @@
...
@@ -985,6 +989,7 @@
(clobber (reg:SI 0))]
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divss")
"bla __divss")
(define_insn "divus_call"
(define_insn "divus_call"
[
(set (reg:SI 3)
[
(set (reg:SI 3)
(udiv:SI (reg:SI 3) (reg:SI 4)))
(udiv:SI (reg:SI 3) (reg:SI 4)))
...
@@ -994,12 +999,14 @@
...
@@ -994,12 +999,14 @@
(clobber (reg:SI 0))]
(clobber (reg:SI 0))]
"! TARGET_POWER && ! TARGET_POWERPC"
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __divus")
"bla __divus")
(define_insn "quoss_call"
(define_insn "quoss_call"
[
(set (reg:SI 3)
[
(set (reg:SI 3)
(div:SI (reg:SI 3) (reg:SI 4)))
(div:SI (reg:SI 3) (reg:SI 4)))
(clobber (match_scratch:SI 0 "=l"))]
(clobber (match_scratch:SI 0 "=l"))]
"! TARGET_POWER && ! TARGET_POWERPC"
"! TARGET_POWER && ! TARGET_POWERPC"
"bla __quoss")
"bla __quoss")
(define_insn "quous_call"
(define_insn "quous_call"
[
(set (reg:SI 3)
[
(set (reg:SI 3)
(udiv:SI (reg:SI 3) (reg:SI 4)))
(udiv:SI (reg:SI 3) (reg:SI 4)))
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment