arm.md (attribute "type"): Rename "simple_alu_imm" to "arlo_imm".

	* config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
	"arlo_imm".  Rename "alu_reg" to "arlo_reg".  Rename "simple_alu_shift" to
	"extend".  Split "alu_shift" into "shift" and "arlo_shift".  Split
	"alu_shift_reg" into "shift_reg" and "arlo_shift_reg".  List types
	in alphabetical order.
	(attribute "core_cycles"): Update for attribute changes.
	(arm_addsi3): Likewise.
	(addsi3_compare0): Likewise.
	(addsi3_compare0_scratch): Likewise.
	(addsi3_compare_op1): Likewise.
	(addsi3_compare_op2): Likewise.
	(compare_addsi2_op0): Likewise.
	(compare_addsi2_op1): Likewise.
	(addsi3_carryin_shift_<optab>): Likewise.
	(subsi3_carryin_shift): Likewise.
	(rsbsi3_carryin_shift): Likewise.
	(arm_subsi3_insn): Likewise.
	(subsi3_compare0): Likewise.
	(subsi3_compare): Likewise.
	(arm_andsi3_insn): Likewise.
	(thumb1_andsi3_insn): Likewise.
	(andsi3_compare0): Likewise.
	(andsi3_compare0_scratch): Likewise.
	(zeroextractsi_compare0_scratch
	(andsi_not_shiftsi_si): Likewise.
	(iorsi3_insn): Likewise.
	(iorsi3_compare0): Likewise.
	(iorsi3_compare0_scratch): Likewise.
	(arm_xorsi3): Likewise.
	(thumb1_xorsi3_insn): Likewise.
	(xorsi3_compare0): Likewise.
	(xorsi3_compare0_scratch): Likewise.
	(satsi_<SAT:code>_shift): Likewise.
	(rrx): Likewise.
	(arm_shiftsi3): Likewise.
	(shiftsi3_compare0): Likewise.
	(not_shiftsi): Likewise.
	(not_shiftsi_compare0): Likewise.
	(not_shiftsi_compare0_scratch): Likewise.
	(arm_one_cmplsi2): Likewise.
	(thumb_one_complsi2): Likewise.
	(notsi_compare0): Likewise.
	(notsi_compare0_scratch): Likewise.
	(thumb1_zero_extendhisi2): Likewise.
	(arm_zero_extendhisi2): Likewise.
	(arm_zero_extendhisi2_v6): Likewise.
	(arm_zero_extendhisi2addsi): Likewise.
	(thumb1_zero_extendqisi2): Likewise.
	(thumb1_zero_extendqisi2_v6): Likewise.
	(arm_zero_extendqisi2): Likewise.
	(arm_zero_extendqisi2_v6): Likewise.
	(arm_zero_extendqisi2addsi): Likewise.
	(thumb1_extendhisi2): Likewise.
	(arm_extendhisi2): Likewise.
	(arm_extendhisi2_v6): Likewise.
	(arm_extendqisi): Likewise.
	(arm_extendqisi_v6): Likewise.
	(arm_extendqisi2addsi): Likewise.
	(thumb1_extendqisi2): Likewise.
	(thumb1_movdi_insn): Likewise.
	(arm_movsi_insn): Likewise.
	(movsi_compare0): Likewise.
	(movhi_insn_arch4): Likewise.
	(movhi_bytes): Likewise.
	(arm_movqi_insn): Likewise.
	(thumb1_movqi_insn): Likewise.
	(arm32_movhf): Likewise.
	(thumb1_movhf): Likewise.
	(arm_movsf_soft_insn): Likewise.
	(thumb1_movsf_insn): Likewise.
	(movdf_soft_insn): Likewise.
	(thumb_movdf_insn): Likewise.
	(arm_cmpsi_insn): Likewise.
	(cmpsi_shiftsi): Likewise.
	(cmpsi_shiftsi_swp): Likewise.
	(arm_cmpsi_negshiftsi_si): Likewise.
	(movsicc_insn): Likewise.
	(movsfcc_soft_insn): Likewise.
	(arith_shiftsi): Likewise.
	(arith_shiftsi_compare0
	(arith_shiftsi_compare0_scratch
	(sub_shiftsi): Likewise.
	(sub_shiftsi_compare0
	(sub_shiftsi_compare0_scratch
	(and_scc): Likewise.
	(cond_move): Likewise.
	(if_plus_move): Likewise.
	(if_move_plus): Likewise.
	(if_move_not): Likewise.
	(if_not_move): Likewise.
	(if_shift_move): Likewise.
	(if_move_shift): Likewise.
	(if_shift_shift): Likewise.
	(if_not_arith): Likewise.
	(if_arith_not): Likewise.
	(cond_move_not): Likewise.
	(thumb1_ashlsi3): Set type attribute.
	(thumb1_ashrsi3): Likewise.
	(thumb1_lshrsi3): Likewise.
	(thumb1_rotrsi3): Likewise.
	(shiftsi3_compare0_scratch): Likewise.
	* config/arm/neon.md (neon_mov<mode>): Update for attribute changes.
	(neon_mov<mode>): Likewise.
	* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute
	changes.
	(thumb2_movsi_insn): Likewise.
	(thumb2_cmpsi_neg_shiftsi): Likewise.
	(thumb2_extendqisi_v6): Likewise.
	(thumb2_zero_extendhisi2_v6): Likewise.
	(thumb2_zero_extendqisi2_v6): Likewise.
	(thumb2_shiftsi3_short): Likewise.
	(thumb2_addsi3_compare0_scratch): Likewise.
	(orsi_not_shiftsi_si): Likewise.
	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
	* config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute
	changes.
	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
	(1020alu_shift_op): Likewise.
	(1020alu_shift_reg_op): Likewise.
	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
	(alu_shift_op): Likewise.
	(alu_shift_reg_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes.
	(11_alu_shift_op): Likewise.
	(11_alu_shift_reg_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
	(9_alu_shift_reg_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes.
	(cortex_a15_alu_shift): Likewise.
	(cortex_a15_alu_shift_reg): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes.
	(cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute
	changes.
	(cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute
	changes.
	(cortex_a7_alu_reg): Likewise.
	(cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes.
	(cortex_a8_alu_shift): Likewise.
	(cortex_a8_alu_shift_reg): Likewise.
	(cortex_a8_mov): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes.
	(cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes.
	* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes.
	(cortex_r4_mov): Likewise.
	(cortex_r4_alu_shift): Likewise.
	(cortex_r4_alu_shift_reg): Likewise.
	* config/arm/fa526.md (526_alu_op): Update for attribute changes.
	(526_alu_shift_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Update for attribute changes.
	* config/arm/fa626te.md (626te_alu_op): Update for attribute changes.
	(626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md (726te_shift_op): Update for attribute changes.
	(726te_alu_op): Likewise.
	(726te_alu_shift_op): Likewise.
	(726te_alu_shift_reg_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
	(mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes.
	(pj4_alu_e1_conds): Likewise.
	(pj4_alu): Likewise.
	(pj4_alu_conds): Likewise.
	(pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes.
	(cortexa7_older_only): Likewise.
	(cortexa7_younger): Likewise.

From-SVN: r201024

gcc/ChangeLog

+2013-07-18  Sofiane Naci  <sofiane.naci@arm.com>
+
+	* config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
+	"arlo_imm".  Rename "alu_reg" to "arlo_reg".  Rename "simple_alu_shift" to
+	"extend".  Split "alu_shift" into "shift" and "arlo_shift".  Split
+	"alu_shift_reg" into "shift_reg" and "arlo_shift_reg".  List types
+	in alphabetical order.
+	(attribute "core_cycles"): Update for attribute changes.
+	(arm_addsi3): Likewise.
+	(addsi3_compare0): Likewise.
+	(addsi3_compare0_scratch): Likewise.
+	(addsi3_compare_op1): Likewise.
+	(addsi3_compare_op2): Likewise.
+	(compare_addsi2_op0): Likewise.
+	(compare_addsi2_op1): Likewise.
+	(addsi3_carryin_shift_<optab>): Likewise.
+	(subsi3_carryin_shift): Likewise.
+	(rsbsi3_carryin_shift): Likewise.
+	(arm_subsi3_insn): Likewise.
+	(subsi3_compare0): Likewise.
+	(subsi3_compare): Likewise.
+	(arm_andsi3_insn): Likewise.
+	(thumb1_andsi3_insn): Likewise.
+	(andsi3_compare0): Likewise.
+	(andsi3_compare0_scratch): Likewise.
+	(zeroextractsi_compare0_scratch
+	(andsi_not_shiftsi_si): Likewise.
+	(iorsi3_insn): Likewise.
+	(iorsi3_compare0): Likewise.
+	(iorsi3_compare0_scratch): Likewise.
+	(arm_xorsi3): Likewise.
+	(thumb1_xorsi3_insn): Likewise.
+	(xorsi3_compare0): Likewise.
+	(xorsi3_compare0_scratch): Likewise.
+	(satsi_<SAT:code>_shift): Likewise.
+	(rrx): Likewise.
+	(arm_shiftsi3): Likewise.
+	(shiftsi3_compare0): Likewise.
+	(not_shiftsi): Likewise.
+	(not_shiftsi_compare0): Likewise.
+	(not_shiftsi_compare0_scratch): Likewise.
+	(arm_one_cmplsi2): Likewise.
+	(thumb_one_complsi2): Likewise.
+	(notsi_compare0): Likewise.
+	(notsi_compare0_scratch): Likewise.
+	(thumb1_zero_extendhisi2): Likewise.
+	(arm_zero_extendhisi2): Likewise.
+	(arm_zero_extendhisi2_v6): Likewise.
+	(arm_zero_extendhisi2addsi): Likewise.
+	(thumb1_zero_extendqisi2): Likewise.
+	(thumb1_zero_extendqisi2_v6): Likewise.
+	(arm_zero_extendqisi2): Likewise.
+	(arm_zero_extendqisi2_v6): Likewise.
+	(arm_zero_extendqisi2addsi): Likewise.
+	(thumb1_extendhisi2): Likewise.
+	(arm_extendhisi2): Likewise.
+	(arm_extendhisi2_v6): Likewise.
+	(arm_extendqisi): Likewise.
+	(arm_extendqisi_v6): Likewise.
+	(arm_extendqisi2addsi): Likewise.
+	(thumb1_extendqisi2): Likewise.
+	(thumb1_movdi_insn): Likewise.
+	(arm_movsi_insn): Likewise.
+	(movsi_compare0): Likewise.
+	(movhi_insn_arch4): Likewise.
+	(movhi_bytes): Likewise.
+	(arm_movqi_insn): Likewise.
+	(thumb1_movqi_insn): Likewise.
+	(arm32_movhf): Likewise.
+	(thumb1_movhf): Likewise.
+	(arm_movsf_soft_insn): Likewise.
+	(thumb1_movsf_insn): Likewise.
+	(movdf_soft_insn): Likewise.
+	(thumb_movdf_insn): Likewise.
+	(arm_cmpsi_insn): Likewise.
+	(cmpsi_shiftsi): Likewise.
+	(cmpsi_shiftsi_swp): Likewise.
+	(arm_cmpsi_negshiftsi_si): Likewise.
+	(movsicc_insn): Likewise.
+	(movsfcc_soft_insn): Likewise.
+	(arith_shiftsi): Likewise.
+	(arith_shiftsi_compare0
+	(arith_shiftsi_compare0_scratch
+	(sub_shiftsi): Likewise.
+	(sub_shiftsi_compare0
+	(sub_shiftsi_compare0_scratch
+	(and_scc): Likewise.
+	(cond_move): Likewise.
+	(if_plus_move): Likewise.
+	(if_move_plus): Likewise.
+	(if_move_not): Likewise.
+	(if_not_move): Likewise.
+	(if_shift_move): Likewise.
+	(if_move_shift): Likewise.
+	(if_shift_shift): Likewise.
+	(if_not_arith): Likewise.
+	(if_arith_not): Likewise.
+	(cond_move_not): Likewise.
+	(thumb1_ashlsi3): Set type attribute.
+	(thumb1_ashrsi3): Likewise.
+	(thumb1_lshrsi3): Likewise.
+	(thumb1_rotrsi3): Likewise.
+	(shiftsi3_compare0_scratch): Likewise.
+	* config/arm/neon.md (neon_mov<mode>): Update for attribute changes.
+	(neon_mov<mode>): Likewise.
+	* config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute
+	changes.
+	(thumb2_movsi_insn): Likewise.
+	(thumb2_cmpsi_neg_shiftsi): Likewise.
+	(thumb2_extendqisi_v6): Likewise.
+	(thumb2_zero_extendhisi2_v6): Likewise.
+	(thumb2_zero_extendqisi2_v6): Likewise.
+	(thumb2_shiftsi3_short): Likewise.
+	(thumb2_addsi3_compare0_scratch): Likewise.
+	(orsi_not_shiftsi_si): Likewise.
+	* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
+	* config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute
+	changes.
+	* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
+	(1020alu_shift_op): Likewise.
+	(1020alu_shift_reg_op): Likewise.
+	* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
+	(alu_shift_op): Likewise.
+	(alu_shift_reg_op): Likewise.
+	* config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes.
+	(11_alu_shift_op): Likewise.
+	(11_alu_shift_reg_op): Likewise.
+	* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
+	(9_alu_shift_reg_op): Likewise.
+	* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes.
+	(cortex_a15_alu_shift): Likewise.
+	(cortex_a15_alu_shift_reg): Likewise.
+	* config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes.
+	(cortex_a5_alu_shift): Likewise.
+	* config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute
+	changes.
+	(cortex_a53_alu_shift): Likewise.
+	* config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute
+	changes.
+	(cortex_a7_alu_reg): Likewise.
+	(cortex_a7_alu_shift): Likewise.
+	* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes.
+	(cortex_a8_alu_shift): Likewise.
+	(cortex_a8_alu_shift_reg): Likewise.
+	(cortex_a8_mov): Likewise.
+	* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes.
+	(cortex_a9_dp_shift): Likewise.
+	* config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes.
+	* config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes.
+	(cortex_r4_mov): Likewise.
+	(cortex_r4_alu_shift): Likewise.
+	(cortex_r4_alu_shift_reg): Likewise.
+	* config/arm/fa526.md (526_alu_op): Update for attribute changes.
+	(526_alu_shift_op): Likewise.
+	* config/arm/fa606te.md (606te_alu_op): Update for attribute changes.
+	* config/arm/fa626te.md (626te_alu_op): Update for attribute changes.
+	(626te_alu_shift_op): Likewise.
+	* config/arm/fa726te.md (726te_shift_op): Update for attribute changes.
+	(726te_alu_op): Likewise.
+	(726te_alu_shift_op): Likewise.
+	(726te_alu_shift_reg_op): Likewise.
+	* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
+	(mp626_alu_shift_op): Likewise.
+	* config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes.
+	(pj4_alu_e1_conds): Likewise.
+	(pj4_alu): Likewise.
+	(pj4_alu_conds): Likewise.
+	(pj4_shift): Likewise.
+	(pj4_shift_conds): Likewise.
+	(pj4_alu_shift): Likewise.
+	(pj4_alu_shift_conds): Likewise.
+	* config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes.
+	(cortexa7_older_only): Likewise.
+	(cortexa7_younger): Likewise.
+
 2013-07-18  David Malcolm  <dmalcolm@redhat.com>
 
 	* ipa-pure-const.c (generate_summary): Rename to...

gcc/config/arm/arm-fixed.md

@@ -385,7 +385,7 @@
    (set_attr "predicable_short_it" "no")
    (set_attr "insn" "sat")
    (set_attr "shift" "1")
-   (set_attr "type" "alu_shift")])
+   (set_attr "type" "arlo_shift")])
 
 (define_insn "arm_usatsihi"
   [(set (match_operand:HI 0 "s_register_operand" "=r")

gcc/config/arm/arm.c

@@ -8653,7 +8653,7 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
 	 instruction we depend on is another ALU instruction, then we may
 	 have to account for an additional stall.  */
       if (shift_opnum != 0
-	  && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
+	  && (attr_type == TYPE_ARLO_SHIFT || attr_type == TYPE_ARLO_SHIFT_REG))
 	{
 	  rtx shifted_operand;
 	  int opno;
@@ -8939,7 +8939,9 @@ cortexa7_older_only (rtx insn)
 
   switch (get_attr_type (insn))
     {
-    case TYPE_ALU_REG:
+    case TYPE_ARLO_REG:
+    case TYPE_SHIFT:
+    case TYPE_SHIFT_REG:
     case TYPE_LOAD_BYTE:
     case TYPE_LOAD1:
     case TYPE_STORE1:
@@ -8985,8 +8987,8 @@ cortexa7_younger (FILE *file, int verbose, rtx insn)
 
   switch (get_attr_type (insn))
     {
-    case TYPE_SIMPLE_ALU_IMM:
-    case TYPE_SIMPLE_ALU_SHIFT:
+    case TYPE_ARLO_IMM:
+    case TYPE_EXTEND:
     case TYPE_BRANCH:
     case TYPE_CALL:
       return true;

gcc/config/arm/arm1020e.md

@@ -66,13 +66,13 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "1020alu_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "1020alu_shift_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "simple_alu_shift,alu_shift"))
+      (eq_attr "type" "extend,arlo_shift"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-register operand
@@ -81,7 +81,7 @@
 ;; the execute stage.
 (define_insn_reservation "1020alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu_shift_reg"))
+      (eq_attr "type" "arlo_shift_reg"))
  "1020a_e*2,1020a_m,1020a_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/arm1026ejs.md

@@ -66,13 +66,13 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "alu_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "alu_shift_op" 1 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "simple_alu_shift,alu_shift"))
+      (eq_attr "type" "extend,arlo_shift"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-register operand
@@ -81,7 +81,7 @@
 ;; the execute stage.
 (define_insn_reservation "alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm1026ejs")
-      (eq_attr "type" "alu_shift_reg"))
+      (eq_attr "type" "arlo_shift_reg"))
  "a_e*2,a_m,a_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/arm1136jfs.md

@@ -75,13 +75,13 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "11_alu_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "11_alu_shift_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "simple_alu_shift,alu_shift"))
+      (eq_attr "type" "extend,arlo_shift"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-register operand
@@ -90,7 +90,7 @@
 ;; the shift stage.
 (define_insn_reservation "11_alu_shift_reg_op" 3
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "alu_shift_reg"))
+      (eq_attr "type" "arlo_shift_reg"))
  "e_1*2,e_2,e_3,e_wb")
 
 ;; alu_ops can start sooner, if there is no shifter dependency

gcc/config/arm/arm926ejs.md

@@ -58,7 +58,7 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "9_alu_op" 1 
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift"))
  "e,m,w")
 
 ;; ALU operations with a shift-by-register operand
@@ -67,7 +67,7 @@
 ;; the execute stage.
 (define_insn_reservation "9_alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm926ejs")
-      (eq_attr "type" "alu_shift_reg"))
+      (eq_attr "type" "arlo_shift_reg"))
  "e*2,m,w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/cortex-a15.md

@@ -61,14 +61,14 @@
 ;; Simple ALU without shift
 (define_insn_reservation "cortex_a15_alu" 2
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "alu_reg,simple_alu_imm")
+       (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
             (eq_attr "neon_type" "none")))
   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
 
 ;; ALU ops with immediate shift
 (define_insn_reservation "cortex_a15_alu_shift" 3
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "simple_alu_shift,alu_shift")
+       (and (eq_attr "type" "extend,arlo_shift")
             (eq_attr "neon_type" "none")))
   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
 	       |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
@@ -76,7 +76,7 @@
 ;; ALU ops with register controlled shift
 (define_insn_reservation "cortex_a15_alu_shift_reg" 3
   (and (eq_attr "tune" "cortexa15")
-       (and (eq_attr "type" "alu_shift_reg")
+       (and (eq_attr "type" "arlo_shift_reg")
 	    (eq_attr "neon_type" "none")))
   "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
    |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\

gcc/config/arm/cortex-a5.md

@@ -58,12 +58,12 @@
 
 (define_insn_reservation "cortex_a5_alu" 2
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "alu_reg,simple_alu_imm"))
+       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
   "cortex_a5_ex1")
 
 (define_insn_reservation "cortex_a5_alu_shift" 2
   (and (eq_attr "tune" "cortexa5")
-       (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+       (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
   "cortex_a5_ex1")
 
 ;; Forwarding path for unshifted operands.

gcc/config/arm/cortex-a53.md

@@ -67,12 +67,12 @@
 
 (define_insn_reservation "cortex_a53_alu" 2
   (and (eq_attr "tune" "cortexa53")
-       (eq_attr "type" "alu_reg,simple_alu_imm"))
+       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
   "cortex_a53_slot_any")
 
 (define_insn_reservation "cortex_a53_alu_shift" 2
   (and (eq_attr "tune" "cortexa53")
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "arlo_shift,arlo_shift_reg"))
   "cortex_a53_slot_any")
 
 ;; Forwarding path for unshifted operands.

gcc/config/arm/cortex-a7.md

@@ -88,8 +88,8 @@
 ;; ALU instruction with an immediate operand can dual-issue.
 (define_insn_reservation "cortex_a7_alu_imm" 2
   (and (eq_attr "tune" "cortexa7")
-       (and (ior (eq_attr "type" "simple_alu_imm")
-                 (ior (eq_attr "type" "simple_alu_shift")
+       (and (ior (eq_attr "type" "arlo_imm")
+                 (ior (eq_attr "type" "extend")
                       (and (eq_attr "insn" "mov")
                            (not (eq_attr "length" "8")))))
             (eq_attr "neon_type" "none")))
@@ -99,13 +99,13 @@
 ;; with a younger immediate-based instruction.
 (define_insn_reservation "cortex_a7_alu_reg" 2
   (and (eq_attr "tune" "cortexa7")
-       (and (eq_attr "type" "alu_reg")
+       (and (eq_attr "type" "arlo_reg,shift,shift_reg")
             (eq_attr "neon_type" "none")))
   "cortex_a7_ex1")
 
 (define_insn_reservation "cortex_a7_alu_shift" 2
   (and (eq_attr "tune" "cortexa7")
-       (and (eq_attr "type" "alu_shift,alu_shift_reg")
+       (and (eq_attr "type" "arlo_shift,arlo_shift_reg")
             (eq_attr "neon_type" "none")))
   "cortex_a7_ex1")
 

gcc/config/arm/cortex-a8.md

@@ -85,7 +85,7 @@
 ;; (source read in E2 and destination available at the end of that cycle).
 (define_insn_reservation "cortex_a8_alu" 2
   (and (eq_attr "tune" "cortexa8")
-       (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm")
+       (ior (and (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
 		      (eq_attr "neon_type" "none"))
 		 (not (eq_attr "insn" "mov,mvn")))
             (eq_attr "insn" "clz")))
@@ -93,13 +93,13 @@
 
 (define_insn_reservation "cortex_a8_alu_shift" 2
   (and (eq_attr "tune" "cortexa8")
-       (and (eq_attr "type" "simple_alu_shift,alu_shift")
+       (and (eq_attr "type" "extend,arlo_shift")
             (not (eq_attr "insn" "mov,mvn"))))
   "cortex_a8_default")
 
 (define_insn_reservation "cortex_a8_alu_shift_reg" 2
   (and (eq_attr "tune" "cortexa8")
-       (and (eq_attr "type" "alu_shift_reg")
+       (and (eq_attr "type" "arlo_shift_reg")
             (not (eq_attr "insn" "mov,mvn"))))
   "cortex_a8_default")
 
@@ -107,7 +107,7 @@
 
 (define_insn_reservation "cortex_a8_mov" 1
   (and (eq_attr "tune" "cortexa8")
-       (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")
+       (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg")
             (eq_attr "insn" "mov,mvn")))
   "cortex_a8_default")
 

gcc/config/arm/cortex-a9.md

@@ -80,9 +80,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
 ;; which can go down E2 without any problem.
 (define_insn_reservation "cortex_a9_dp" 2
   (and (eq_attr "tune" "cortexa9")
-         (ior (and (eq_attr "type" "alu_reg,simple_alu_imm")
+         (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
                         (eq_attr "neon_type" "none"))
-	      (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
+	      (and (and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
 			(eq_attr "insn" "mov"))
                  (eq_attr "neon_type" "none"))))
   "cortex_a9_p0_default|cortex_a9_p1_default")
@@ -90,7 +90,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
 ;; An instruction using the shifter will go down E1.
 (define_insn_reservation "cortex_a9_dp_shift" 3
    (and (eq_attr "tune" "cortexa9")
-	(and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
+	(and (eq_attr "type" "arlo_shift_reg,extend,arlo_shift")
 	     (not (eq_attr "insn" "mov"))))
    "cortex_a9_p0_shift | cortex_a9_p1_shift")
 

gcc/config/arm/cortex-m4.md

@@ -31,8 +31,8 @@
 ;; ALU and multiply is one cycle.
 (define_insn_reservation "cortex_m4_alu" 1
   (and (eq_attr "tune" "cortexm4")
-       (ior (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,\
-                             alu_shift,alu_shift_reg")
+       (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
+                             arlo_shift,arlo_shift_reg")
 	    (ior (eq_attr "mul32" "yes")
 		 (eq_attr "mul64" "yes"))))
   "cortex_m4_ex")

gcc/config/arm/cortex-r4.md

@@ -78,24 +78,24 @@
 ;; for the purposes of the dual-issue constraints above.
 (define_insn_reservation "cortex_r4_alu" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (and (eq_attr "type" "alu_reg,simple_alu_imm")
+       (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
             (not (eq_attr "insn" "mov"))))
   "cortex_r4_alu")
 
 (define_insn_reservation "cortex_r4_mov" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (and (eq_attr "type" "alu_reg,simple_alu_imm")
+       (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
             (eq_attr "insn" "mov")))
   "cortex_r4_mov")
 
 (define_insn_reservation "cortex_r4_alu_shift" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (eq_attr "type" "simple_alu_shift,alu_shift"))
+       (eq_attr "type" "extend,arlo_shift"))
   "cortex_r4_alu")
 
 (define_insn_reservation "cortex_r4_alu_shift_reg" 2
   (and (eq_attr "tune_cortexr4" "yes")
-       (eq_attr "type" "alu_shift_reg"))
+       (eq_attr "type" "arlo_shift_reg"))
   "cortex_r4_alu_shift_reg")
 
 ;; An ALU instruction followed by an ALU instruction with no early dep.

gcc/config/arm/fa526.md

@@ -62,12 +62,12 @@
 ;; ALU operations
 (define_insn_reservation "526_alu_op" 1
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
  "fa526_core")
 
 (define_insn_reservation "526_alu_shift_op" 2
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+      (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
  "fa526_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/fa606te.md

@@ -62,7 +62,7 @@
 ;; ALU operations
 (define_insn_reservation "606te_alu_op" 1
  (and (eq_attr "tune" "fa606te")
-      (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,arlo_shift_reg"))
  "fa606te_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/fa626te.md

@@ -68,12 +68,12 @@
 ;; ALU operations
 (define_insn_reservation "626te_alu_op" 1
  (and (eq_attr "tune" "fa626,fa626te")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
  "fa626te_core")
 
 (define_insn_reservation "626te_alu_shift_op" 2
  (and (eq_attr "tune" "fa626,fa626te")
-      (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+      (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
  "fa626te_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/fa726te.md

@@ -85,7 +85,7 @@
 ;; Other ALU instructions 2 cycles.
 (define_insn_reservation "726te_alu_op" 1
  (and (eq_attr "tune" "fa726te")
-      (and (eq_attr "type" "alu_reg,simple_alu_imm")
+      (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
            (not (eq_attr "insn" "mov,mvn"))))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 
@@ -95,13 +95,13 @@
 ;; it takes 3 cycles.
 (define_insn_reservation "726te_alu_shift_op" 3
  (and (eq_attr "tune" "fa726te")
-      (and (eq_attr "type" "simple_alu_shift,alu_shift")
+      (and (eq_attr "type" "extend,arlo_shift")
            (not (eq_attr "insn" "mov,mvn"))))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 
 (define_insn_reservation "726te_alu_shift_reg_op" 3
  (and (eq_attr "tune" "fa726te")
-      (and (eq_attr "type" "alu_shift_reg")
+      (and (eq_attr "type" "arlo_shift_reg")
            (not (eq_attr "insn" "mov,mvn"))))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/fmp626.md

@@ -63,12 +63,12 @@
 ;; ALU operations
 (define_insn_reservation "mp626_alu_op" 1
  (and (eq_attr "tune" "fmp626")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
  "fmp626_core")
 
 (define_insn_reservation "mp626_alu_shift_op" 2
  (and (eq_attr "tune" "fmp626")
-      (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg"))
+      (eq_attr "type" "extend,arlo_shift,arlo_shift_reg"))
  "fmp626_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

gcc/config/arm/marvell-pj4.md

@@ -41,54 +41,54 @@
 
 (define_insn_reservation "pj4_alu_e1" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "simple_alu_imm,alu_reg")
+       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
        (not (eq_attr "conds" "set"))
        (eq_attr "insn" "mov,mvn"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_e1_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "simple_alu_imm,alu_reg")
+       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
        (eq_attr "conds" "set")
        (eq_attr "insn" "mov,mvn"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "simple_alu_imm,alu_reg")
+       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
        (not (eq_attr "conds" "set"))
        (not (eq_attr "insn" "mov,mvn")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "simple_alu_imm,alu_reg")
+       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
        (eq_attr "conds" "set")
        (not (eq_attr "insn" "mov,mvn")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
+       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
        (not (eq_attr "conds" "set"))
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
+       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend")
        (eq_attr "conds" "set")
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
        (not (eq_attr "conds" "set"))
-       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
+       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "conds" "set")
-       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
+       (eq_attr "type" "arlo_shift,arlo_shift_reg,extend"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_bypass 2 "pj4_alu_shift,pj4_shift"

gcc/config/arm/neon.md

@@ -61,7 +61,7 @@
     }
 }
  [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
-  (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2")
+  (set_attr "type" "*,f_stored,*,f_loadd,*,*,arlo_reg,load2,store2")
   (set_attr "insn" "*,*,*,*,*,*,mov,*,*")
   (set_attr "length" "4,4,4,4,4,4,8,8,8")
   (set_attr "arm_pool_range"     "*,*,*,1020,*,*,*,1020,*")
@@ -107,7 +107,7 @@
 }
   [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
                           neon_mrrc,neon_mcr_2_mcrr,*,*,*")
-   (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4")
+   (set_attr "type" "*,*,*,*,*,*,arlo_reg,load4,store4")
    (set_attr "insn" "*,*,*,*,*,*,mov,*,*")
    (set_attr "length" "4,8,4,8,8,8,16,8,16")
    (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")

gcc/config/arm/thumb2.md

@@ -35,7 +35,7 @@
   "bic%?\\t%0, %1, %2%S4"
   [(set_attr "predicable" "yes")
    (set_attr "shift" "2")
-   (set_attr "type" "alu_shift")]
+   (set_attr "type" "arlo_shift")]
 )
 
 (define_insn_and_split "*thumb2_smaxsi3"
@@ -283,7 +283,7 @@
    ldr%?\\t%0, %1
    str%?\\t%1, %0
    str%?\\t%1, %0"
-  [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,*,load1,load1,store1,store1")
+  [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1")
    (set_attr "length" "2,4,2,4,4,4,4,4,4")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
@@ -336,7 +336,7 @@
   "cmn%?\\t%0, %1%S3"
   [(set_attr "conds" "set")
    (set_attr "shift" "1")
-   (set_attr "type" "alu_shift")]
+   (set_attr "type" "arlo_shift")]
 )
 
 (define_insn_and_split "*thumb2_mov_scc"
@@ -815,7 +815,7 @@
   "@
    sxtb%?\\t%0, %1
    ldr%(sb%)\\t%0, %1"
-  [(set_attr "type" "simple_alu_shift,load_byte")
+  [(set_attr "type" "extend,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -828,7 +828,7 @@
   "@
    uxth%?\\t%0, %1
    ldr%(h%)\\t%0, %1"
-  [(set_attr "type" "simple_alu_shift,load_byte")
+  [(set_attr "type" "extend,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -841,7 +841,7 @@
   "@
    uxtb%(%)\\t%0, %1
    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
-  [(set_attr "type" "simple_alu_shift,load_byte")
+  [(set_attr "type" "extend,load_byte")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,4094")
    (set_attr "neg_pool_range" "*,250")]
@@ -933,8 +933,8 @@
    (set_attr "shift" "1")
    (set_attr "length" "2")
    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
-		      (const_string "alu_shift")
-		      (const_string "alu_shift_reg")))]
+		      (const_string "arlo_shift")
+		      (const_string "arlo_shift_reg")))]
 )
 
 (define_insn "*thumb2_mov<mode>_shortim"
@@ -1056,7 +1056,7 @@
   "
   [(set_attr "conds" "set")
    (set_attr "length" "2,2,4,4")
-   (set_attr "type"   "simple_alu_imm,*,simple_alu_imm,*")]
+   (set_attr "type"   "arlo_imm,*,arlo_imm,*")]
 )
 
 (define_insn "*thumb2_mulsi_short"
@@ -1180,7 +1180,7 @@
   "orn%?\\t%0, %1, %2%S4"
   [(set_attr "predicable" "yes")
    (set_attr "shift" "2")
-   (set_attr "type" "alu_shift")]
+   (set_attr "type" "arlo_shift")]
 )
 
 (define_peephole2

gcc/config/arm/vfp.md

@@ -53,7 +53,7 @@
     }
   "
   [(set_attr "predicable" "yes")
-   (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+   (set_attr "type" "*,*,arlo_imm,arlo_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
    (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")