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riscv-gcc-1
Commit 00188daa by Uros Bizjak
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i386.md (X87MODEF12, SSEMODEF): Remove mode iterators. 

2007-09-09  Uros Bizjak  <ubizjak@gmail.com>

        * config/i386/i386.md (X87MODEF12, SSEMODEF): Remove mode iterators.
        Substitute all uses with ...
        (MODEF): New mode iterator.

        (*cmpfp_<mode>_cc): Remove operand constraints from pre-regalloc
        define_insn_and_split splitter pattern.
        (fix_trunc<mode>_fisttp_i387_1): Ditto.
        (*fix_trunc<mode>_i387_1): Ditto.
        (*fistdi2_1): Ditto.
        (*fist<mode>2_1): Ditto.
        (frndintxf2_floor): Ditto.
        (*fist<mode>2_floor_1): Ditto.
        (frndintxf2_ceil): Ditto.
        (*fist<mode>2_ceil_1): Ditto.
        (frndintxf2_trunc): Ditto.
        (frndintxf2_mask_pm): Ditto.

        (prologue): Use (const_int 0) as never generated filler insn.
        (epilogue): Ditto.
        (sibcall_epilogue): Ditto.
        (eh_return_si): Ditto.
        (eh_return_di): Ditto.

        (add<mode>3): Rename from adddf3 and addsf3.  Macroize expander
        using MODEF mode iterator.
        (sub<mode>3): Rename from subdf3 and subsf3.  Macroize expander
        using MODEF mode iterator.
        (mul<mode>3): Rename from muldf3 and mulsf3.  Macroize expander
        using MODEF mode iterator.
        (nearbyint<mode>2): Rename from nearbyintdf2 and nearbyintsf2.
        Macroize expander using MODEF mode iterator.

        (zero_extendsidi2): Remove operand constraints from expander.
        (smuldi3_highpart): Ditto.
        (indirect_jump): Ditto.
        (tablejump): Ditto.
        (rsqrtsf2): Ditto.
        * config/i386/sse.md (storentv4sf): Ditto.
        (storentv2df): Ditto.
        (storentv2di): Ditto.
        (storentsi): Ditto.
        (sse2_cvtpd2ps): Ditto.
        (vec_interleave_highv16qi): Ditto.
        (vec_interleave_lowv16qi): Ditto.
        (vec_interleave_highv8hi): Ditto.
        (vec_interleave_lowv8hi): Ditto.
        (vec_interleave_highv4si): Ditto.
        (vec_interleave_lowv4si): Ditto.
        (vec_interleave_highv2di): Ditto.
        (vec_interleave_lowv2di): Ditto.
        (sse2_maskmovdqu): Ditto.
        * config/i386/mmx.md (mmx_maskmovq): Ditto.

From-SVN: r128290
parent 805e2059
Showing with 96 additions and 41 deletions
gcc/ChangeLog
2007-09-09 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (X87MODEF12, SSEMODEF): Remove mode iterators.
Substitute all uses with ...
(MODEF): New mode iterator.
(*cmpfp_<mode>_cc): Remove operand constraints from pre-regalloc
define_insn_and_split splitter pattern.
(fix_trunc<mode>_fisttp_i387_1): Ditto.
(*fix_trunc<mode>_i387_1): Ditto.
(*fistdi2_1): Ditto.
(*fist<mode>2_1): Ditto.
(frndintxf2_floor): Ditto.
(*fist<mode>2_floor_1): Ditto.
(frndintxf2_ceil): Ditto.
(*fist<mode>2_ceil_1): Ditto.
(frndintxf2_trunc): Ditto.
(frndintxf2_mask_pm): Ditto.
(prologue): Use (const_int 0) as never generated filler insn.
(epilogue): Ditto.
(sibcall_epilogue): Ditto.
(eh_return_si): Ditto.
(eh_return_di): Ditto.
(add<mode>3): Rename from adddf3 and addsf3. Macroize expander
using MODEF mode iterator.
(sub<mode>3): Rename from subdf3 and subsf3. Macroize expander
using MODEF mode iterator.
(mul<mode>3): Rename from muldf3 and mulsf3. Macroize expander
using MODEF mode iterator.
(nearbyint<mode>2): Rename from nearbyintdf2 and nearbyintsf2.
Macroize expander using MODEF mode iterator.
(zero_extendsidi2): Remove operand constraints from expander.
(smuldi3_highpart): Ditto.
(indirect_jump): Ditto.
(tablejump): Ditto.
(rsqrtsf2): Ditto.
* config/i386/sse.md (storentv4sf): Ditto.
(storentv2df): Ditto.
(storentv2di): Ditto.
(storentsi): Ditto.
(sse2_cvtpd2ps): Ditto.
(vec_interleave_highv16qi): Ditto.
(vec_interleave_lowv16qi): Ditto.
(vec_interleave_highv8hi): Ditto.
(vec_interleave_lowv8hi): Ditto.
(vec_interleave_highv4si): Ditto.
(vec_interleave_lowv4si): Ditto.
(vec_interleave_highv2di): Ditto.
(vec_interleave_lowv2di): Ditto.
(sse2_maskmovdqu): Ditto.
* config/i386/mmx.md (mmx_maskmovq): Ditto.
2007-09-09 Ira Rosen <irar@il.ibm.com> 2007-09-09 Ira Rosen <irar@il.ibm.com>
* tree-vectorizer.h (enum vect_def_type): Start enumeration from 1. * tree-vectorizer.h (enum vect_def_type): Start enumeration from 1.
...@@ -197,12 +252,12 @@ ...@@ -197,12 +252,12 @@
2007-09-08 Uros Bizjak <ubizjak@gmail.com> 2007-09-08 Uros Bizjak <ubizjak@gmail.com>
PR target/33329 PR target/33329
PR target/26449 PR rtl-optimization/26449
* config/i386/sse.md (mulv4si3): Do not expand sse2 sequence. * config/i386/sse.md (mulv4si3): Do not expand sse2 sequence.
(*sse2_mulv4si3): New define_insn_and_split pattern. Split insn in (*sse2_mulv4si3): New define_insn_and_split pattern. Split insn in
split1 pass. split1 pass.
(mulv16qi3): Implement as define_insn_and_split pattern instead of (mulv16qi3): Implement as define_insn_and_split pattern instead of
define_expand, to split insn in split1 pass. define_expand. Split insn in split1 pass.
(mulv2di3): Ditto. (mulv2di3): Ditto.
2007-09-08 Dorit Nuzman <dorit@il.ibm.com> 2007-09-08 Dorit Nuzman <dorit@il.ibm.com>
...@@ -320,8 +375,8 @@ ...@@ -320,8 +375,8 @@
2007-09-07 Dorit Nuzman <dorit@il.ibm.com> 2007-09-07 Dorit Nuzman <dorit@il.ibm.com>
PR tree-optimization/33299 PR tree-optimization/33299
* tree-vect-transform.c (vect_create_epilog_for_reduction): Update uses * tree-vect-transform.c (vect_create_epilog_for_reduction): Update
for all relevant loop-exit phis, not just the first. uses for all relevant loop-exit phis, not just the first.
2007-09-07 Richard Guenther <rguenther@suse.de> 2007-09-07 Richard Guenther <rguenther@suse.de>
gcc/config/i386/mmx.md
...@@ -1354,8 +1354,8 @@ ...@@ -1354,8 +1354,8 @@
(define_expand "mmx_maskmovq" (define_expand "mmx_maskmovq"
[(set (match_operand:V8QI 0 "memory_operand" "") [(set (match_operand:V8QI 0 "memory_operand" "")
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "")
(match_operand:V8QI 2 "register_operand" "y") (match_operand:V8QI 2 "register_operand" "")
(match_dup 0)] (match_dup 0)]
UNSPEC_MASKMOV))] UNSPEC_MASKMOV))]
"TARGET_SSE || TARGET_3DNOW_A" "TARGET_SSE || TARGET_3DNOW_A"
......
gcc/config/i386/sse.md
...@@ -315,29 +315,29 @@ ...@@ -315,29 +315,29 @@
; define patterns for other modes that would expand to several insns. ; define patterns for other modes that would expand to several insns.
(define_expand "storentv4sf" (define_expand "storentv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m") [(set (match_operand:V4SF 0 "memory_operand" "")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")]
UNSPEC_MOVNT))] UNSPEC_MOVNT))]
"TARGET_SSE" "TARGET_SSE"
"") "")
(define_expand "storentv2df" (define_expand "storentv2df"
[(set (match_operand:V2DF 0 "memory_operand" "=m") [(set (match_operand:V2DF 0 "memory_operand" "")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "")]
UNSPEC_MOVNT))] UNSPEC_MOVNT))]
"TARGET_SSE2" "TARGET_SSE2"
"") "")
(define_expand "storentv2di" (define_expand "storentv2di"
[(set (match_operand:V2DI 0 "memory_operand" "=m") [(set (match_operand:V2DI 0 "memory_operand" "")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")] (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "")]
UNSPEC_MOVNT))] UNSPEC_MOVNT))]
"TARGET_SSE2" "TARGET_SSE2"
"") "")
(define_expand "storentsi" (define_expand "storentsi"
[(set (match_operand:SI 0 "memory_operand" "=m") [(set (match_operand:SI 0 "memory_operand" "")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")] (unspec:SI [(match_operand:SI 1 "register_operand" "")]
UNSPEC_MOVNT))] UNSPEC_MOVNT))]
"TARGET_SSE2" "TARGET_SSE2"
"") "")
...@@ -2282,7 +2282,7 @@ ...@@ -2282,7 +2282,7 @@
[(set (match_operand:V4SF 0 "register_operand" "") [(set (match_operand:V4SF 0 "register_operand" "")
(vec_concat:V4SF (vec_concat:V4SF
(float_truncate:V2SF (float_truncate:V2SF
(match_operand:V2DF 1 "nonimmediate_operand" "xm")) (match_operand:V2DF 1 "nonimmediate_operand" ""))
(match_dup 2)))] (match_dup 2)))]
"TARGET_SSE2" "TARGET_SSE2"
"operands[2] = CONST0_RTX (V2SFmode);") "operands[2] = CONST0_RTX (V2SFmode);")
...@@ -4075,11 +4075,11 @@ ...@@ -4075,11 +4075,11 @@
}) })
(define_expand "vec_interleave_highv16qi" (define_expand "vec_interleave_highv16qi"
[(set (match_operand:V16QI 0 "register_operand" "=x") [(set (match_operand:V16QI 0 "register_operand" "")
(vec_select:V16QI (vec_select:V16QI
(vec_concat:V32QI (vec_concat:V32QI
(match_operand:V16QI 1 "register_operand" "0") (match_operand:V16QI 1 "register_operand" "")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")) (match_operand:V16QI 2 "nonimmediate_operand" ""))
(parallel [(const_int 8) (const_int 24) (parallel [(const_int 8) (const_int 24)
(const_int 9) (const_int 25) (const_int 9) (const_int 25)
(const_int 10) (const_int 26) (const_int 10) (const_int 26)
...@@ -4095,11 +4095,11 @@ ...@@ -4095,11 +4095,11 @@
}) })
(define_expand "vec_interleave_lowv16qi" (define_expand "vec_interleave_lowv16qi"
[(set (match_operand:V16QI 0 "register_operand" "=x") [(set (match_operand:V16QI 0 "register_operand" "")
(vec_select:V16QI (vec_select:V16QI
(vec_concat:V32QI (vec_concat:V32QI
(match_operand:V16QI 1 "register_operand" "0") (match_operand:V16QI 1 "register_operand" "")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")) (match_operand:V16QI 2 "nonimmediate_operand" ""))
(parallel [(const_int 0) (const_int 16) (parallel [(const_int 0) (const_int 16)
(const_int 1) (const_int 17) (const_int 1) (const_int 17)
(const_int 2) (const_int 18) (const_int 2) (const_int 18)
...@@ -4115,11 +4115,11 @@ ...@@ -4115,11 +4115,11 @@
}) })
(define_expand "vec_interleave_highv8hi" (define_expand "vec_interleave_highv8hi"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "=")
(vec_select:V8HI (vec_select:V8HI
(vec_concat:V16HI (vec_concat:V16HI
(match_operand:V8HI 1 "register_operand" "0") (match_operand:V8HI 1 "register_operand" "")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")) (match_operand:V8HI 2 "nonimmediate_operand" ""))
(parallel [(const_int 4) (const_int 12) (parallel [(const_int 4) (const_int 12)
(const_int 5) (const_int 13) (const_int 5) (const_int 13)
(const_int 6) (const_int 14) (const_int 6) (const_int 14)
...@@ -4131,11 +4131,11 @@ ...@@ -4131,11 +4131,11 @@
}) })
(define_expand "vec_interleave_lowv8hi" (define_expand "vec_interleave_lowv8hi"
[(set (match_operand:V8HI 0 "register_operand" "=x") [(set (match_operand:V8HI 0 "register_operand" "")
(vec_select:V8HI (vec_select:V8HI
(vec_concat:V16HI (vec_concat:V16HI
(match_operand:V8HI 1 "register_operand" "0") (match_operand:V8HI 1 "register_operand" "")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")) (match_operand:V8HI 2 "nonimmediate_operand" ""))
(parallel [(const_int 0) (const_int 8) (parallel [(const_int 0) (const_int 8)
(const_int 1) (const_int 9) (const_int 1) (const_int 9)
(const_int 2) (const_int 10) (const_int 2) (const_int 10)
...@@ -4147,11 +4147,11 @@ ...@@ -4147,11 +4147,11 @@
}) })
(define_expand "vec_interleave_highv4si" (define_expand "vec_interleave_highv4si"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "")
(vec_select:V4SI (vec_select:V4SI
(vec_concat:V8SI (vec_concat:V8SI
(match_operand:V4SI 1 "register_operand" "0") (match_operand:V4SI 1 "register_operand" "")
(match_operand:V4SI 2 "nonimmediate_operand" "xm")) (match_operand:V4SI 2 "nonimmediate_operand" ""))
(parallel [(const_int 2) (const_int 6) (parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))] (const_int 3) (const_int 7)])))]
"TARGET_SSE2" "TARGET_SSE2"
...@@ -4161,11 +4161,11 @@ ...@@ -4161,11 +4161,11 @@
}) })
(define_expand "vec_interleave_lowv4si" (define_expand "vec_interleave_lowv4si"
[(set (match_operand:V4SI 0 "register_operand" "=x") [(set (match_operand:V4SI 0 "register_operand" "")
(vec_select:V4SI (vec_select:V4SI
(vec_concat:V8SI (vec_concat:V8SI
(match_operand:V4SI 1 "register_operand" "0") (match_operand:V4SI 1 "register_operand" "")
(match_operand:V4SI 2 "nonimmediate_operand" "xm")) (match_operand:V4SI 2 "nonimmediate_operand" ""))
(parallel [(const_int 0) (const_int 4) (parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))] (const_int 1) (const_int 5)])))]
"TARGET_SSE2" "TARGET_SSE2"
...@@ -4175,11 +4175,11 @@ ...@@ -4175,11 +4175,11 @@
}) })
(define_expand "vec_interleave_highv2di" (define_expand "vec_interleave_highv2di"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "")
(vec_select:V2DI (vec_select:V2DI
(vec_concat:V4DI (vec_concat:V4DI
(match_operand:V2DI 1 "register_operand" "0") (match_operand:V2DI 1 "register_operand" "")
(match_operand:V2DI 2 "nonimmediate_operand" "xm")) (match_operand:V2DI 2 "nonimmediate_operand" ""))
(parallel [(const_int 1) (parallel [(const_int 1)
(const_int 3)])))] (const_int 3)])))]
"TARGET_SSE2" "TARGET_SSE2"
...@@ -4189,11 +4189,11 @@ ...@@ -4189,11 +4189,11 @@
}) })
(define_expand "vec_interleave_lowv2di" (define_expand "vec_interleave_lowv2di"
[(set (match_operand:V2DI 0 "register_operand" "=x") [(set (match_operand:V2DI 0 "register_operand" "")
(vec_select:V2DI (vec_select:V2DI
(vec_concat:V4DI (vec_concat:V4DI
(match_operand:V2DI 1 "register_operand" "0") (match_operand:V2DI 1 "register_operand" "")
(match_operand:V2DI 2 "nonimmediate_operand" "xm")) (match_operand:V2DI 2 "nonimmediate_operand" ""))
(parallel [(const_int 0) (parallel [(const_int 0)
(const_int 2)])))] (const_int 2)])))]
"TARGET_SSE2" "TARGET_SSE2"
...@@ -5234,8 +5234,8 @@ ...@@ -5234,8 +5234,8 @@
(define_expand "sse2_maskmovdqu" (define_expand "sse2_maskmovdqu"
[(set (match_operand:V16QI 0 "memory_operand" "") [(set (match_operand:V16QI 0 "memory_operand" "")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
(match_operand:V16QI 2 "register_operand" "x") (match_operand:V16QI 2 "register_operand" "")
(match_dup 0)] (match_dup 0)]
UNSPEC_MASKMOV))] UNSPEC_MASKMOV))]
"TARGET_SSE2" "TARGET_SSE2"
......
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