The vsel instruction is a bit-wise select instruction.  Using an
IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being
generated in the combine pass.

With the patch the pattern is written using bit operations.  However,
I've just noticed that the manual still demands a fixed point mode for
AND/IOR and friends although several targets emit bit ops on floating
point vectors (including i386, Power, and s390). So I assume this is a
safe thing to do?!

gcc/ChangeLog:

2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>

	PR target/94613
	* config/s390/s390-builtin-types.def: Add 3 new function modes.
	* config/s390/s390-builtins.def: Add mode dependent low-level
	builtin and map the overloaded builtins to these.
	* config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
	("vsel<V_HW"): ... this and rewrite the pattern with bitops.

gcc/testsuite/ChangeLog:

2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>

	PR target/94613
	* gcc.target/s390/zvector/pr94613.c: New test.
	* gcc.target/s390/zvector/vec_sel-1.c: New test.